This paper presents a new class of Switched Tank Converters (abbreviated as STCs) for high efficiency high density non-isolated DC-DC applications where large voltage step down (up) ratios are required. Distinguished from switched capacitor converters, the STCs uniquely employ LC resonant tanks to partially replace the flying capacitors for energy transfer. Full soft charging, soft switching and minimal device voltage stresses are achieved under all operating conditions. The STCs feature very high efficiency, power density and robustness against component non-idealities over a wide range of operating conditions. Furthermore, thanks to the full resonant operation, multiple STCs can operate in parallel with inherent droop current sharing, offering the best scalability and control simplicity. These attributes make STC a disruptive and robust technology viable for industry's high volume adoption. A novel equivalent DCX building block principle is introduced to simplify the analysis of STC. A 98.9% efficiency STC product evaluation board (4-to-1, 650W) has been developed and demonstrated for the next-generation of 48V bus conversion for data center servers.

In order to increase the efficiency of modern microprocessors power supplies used in data centers, the 48-V dc distribution bus is gaining growing attention. For such applications, voltage regulation modules (VRMs) are currently obtained using two-stage conversion systems with an intermediate 12-V dc bus. This paper presents an innovative single-stage approach for the 48-V VRM based on a quasi-resonant constant on-time (COT) operation. The proposed topology inherently integrates the multiphase approach, providing fast phase shedding and flat high-efficiency curves even at light load conditions. This is a unique advantage, usually not available in the two-stage approach, that is very important in server architectures, where high efficiency is required even at light load conditions. The paper analyses the circuit topology, and proposes a control architecture for fast transient response, including the current sharing capabilities, and a solution for implementing the integrated magnetics. The digital controller has been implemented in 0.16-μ m lithography together with a digital pulse-width-modulation with a 195 ps resolution, and a 40 MS/s, 7-bit ADC. Experimental results show an efficiency of 93.1% for a 250 A, 1.8 V VRM, and of 93.2% for a 102 A, 1.2-V double data rate (DDR) power supply.

This letter proposes a time-optimal digital controller for the phase shedding (PS) in multiphase buck converters. PS is an established technique to improve the efficiency of multiphase converters at light load by changing the active number of phases depending on the load-current level. In order to minimize the output-voltage deviation and the transient time during PS, a minimum time algorithm is investigated. The proposed technique is insensitive to the power stage parameters, as its operation relies only on a feedforward action, depending on the steady-state duty cycle and the number of phases to be turned on or turned off. The proposed approach is validated through experimental tests on a synchronous buck converter.

As the power required by modern data center processors increases, the power architecture must be adapted; for example, 48 V distribution voltage allows to reduce copper losses by a factor 16 with respect to the use of traditional 12 V power architecture. In order to generate the required processor core voltage, a two-stage approach is usually preferred, where the intermediate bus voltage is generated using an unregulated resonant dc–dc converter as, for instance, an LLC converter. Compared to LLCs , hybrid resonant switched-capacitor converters (ReSCCs) make it possible to achieve large voltage conversion ratios without the need of high turns ratio transformers. In this letter, a novel hybrid ReSCC that performs a 48–3.4 V direct conversion is presented. A prototype of the proposed converter has been implemented, capable of providing a continuous output power of 440 W with a maximum efficiency of 96.3% at 30 A load current.

In dc microgrids, droop control is widely employed in power converters interfacing distributed energy resources and common dc bus for automatic power sharing. In order to limit the dc bus voltage variations even during the load transient conditions, it is necessary to shape the output impedance of droop-controlled converters to be always lower than the dc resistive value. A commonly used way is to install bulky output capacitance, which not only increases the system cost, size and weight, but also generates higher short-circuit fault currents. In order to avoid large output capacitance, this paper proposes a design approach for droop-controlled converters, including the selection criterion of the output capacitance and the design of the droop coefficient. Herein, the required output capacitance is calculated based on the dc droop coefficient and the voltage control bandwidth. The droop coefficient is designed as a frequency-dependent term instead of a constant value. As a result, the desired output impedance can be obtained with a much smaller output capacitance. The proposed design strategy is applied to buck and boost converters and validated by experimental results performed on a buck-based and a boost-based dc microgrid prototype, respectively.

This letter presents a linearization technique for multisampled pulsewidth modulators (MSPWMs) employed in digitally controlled dc-dc converters. MSPWMs, i.e., PWMs operated at a sampling rate strictly higher than the switching frequency, greatly reduce the significant small-signal phase lag exhibited by conventional single-sampled PWMs, thus enabling for high-bandwidth design. On the other hand, the increased sampling frequency generates nonlinear phenomena known as sampling-induced dead bands, which represent zero differential gain regions in the modulator transcharacteristic that degrade the system closed-loop operation. This letter proposes a correction algorithm that allows for dead band removal, thus linearizing the PWM behavior, while still retaining the multisampling benefits. This result is achieved by a simple solution that can be easily implemented with simple hardware requirements. Simulation and experimental results on a dc-dc synchronous buck converter are provided to show the effectiveness and overall simplicity of the proposed solution.