Despite decades of R&D, the single-transistor (1-T) memory cell based on ferroelectric-gated Field-Effect-Transistor (FeFET) has failed to commercialize as of this writing, largely due to the inadequate retention time. The recent advent of the HfO 2 -based ferroelectrics, however, promises to change that. The fundamental reasons for this change, which hinges on the relatively large coercive fields (E c 's) of HfO 2 -based ferroelectrics, will be discussed. On the other hand, the large Ec's also causes endurance problems, which is a major reliability concern. This reliability concern is the other key topic covered in this paper.

Photoluminescence intensity (PL-I) data are presented for 22 dielectric/GaAs systems investigated for MOSFET applications. The PL-I technique has been identified as a most useful and reliable tool for screening dielectric/GaAs interfaces and has been instrumental in the identification of a device quality dielectric/GaAs interface: in situ deposited Ga₂O₃ on GaAs. The early discovery of such an interface has allowed us to focus resources and to succeed to manufacture GaAs MOSFETs which perform in line with theoretical model predictions after more than 40 years of failed attempts. It is strongly recommended to extend the technique to the investigation of CMOS relevant channel materials such as InGaAs.

The channel length dependence of the random telegraph signal (RTS) in a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) has been investigated both theoretically and experimentally. The key result is that, for a given surface potential, the RTS amplitude is proportional to 1/L/sup 2/, where L is the channel length, provided the contribution of the mobility fluctuation is much smaller than that of the carrier number fluctuation. A special test structure, consisting of a series combination of MOSFET's, is used to experimentally determine this channel length dependence, and good agreement with our simple theory is obtained.

The properties of metal-nitride-Si (MNS) capacitors in which the silicon nitride layer is produced by the jet vapor deposition (JVD) technique at room temperature are reported. Despite the room-temperature deposition, the electrical properties of these devices are far better than any previously reported MNS capacitors. Especially remarkable is the low density of interface traps (D/sub it/<5*10/sup 10//cm/sup 2/-eV near midgap). In addition, these MNS capacitors are highly resistant to damage caused by hot electrons and ionizing radiation.

From a systematic study of the hot-carrier-induced degradation in fully depleted submicrometer NMOS/SIMOX as a function of front- and back-gate biases during stress, the authors found that the apparent changes of the front-channel transistor parameters, measured at grounded back gate, could be largely attributed to the virtual back-gate bias effect arising from the trapped charge in the buried oxide. The strong dependence of carrier injection at the back interface on the back-gate bias and its resulting effect on the front-channel transistor parameters are also presented.<>