Software testing is a crucial yet time-consuming aspect of software development. Writing comprehensive unit tests that accurately verify whether a function or an entire program behaves as intended requires considerable effort from developers, particularly when handling numerous edge cases. This study explores how Large Language Models (LLMs) can streamline this process by automatically generating effective unit tests. We evaluate various LLMs on their capability to interpret problem specifications, analyze source code across multiple programming languages, and generate suitable test cases. The effectiveness of these test cases is assessed using the Pass@1 and line coverage metrics. Our findings reveal that LLMs perform significantly better when provided with both the problem description and the corresponding solution code, particularly in the C programming language. Additionally, we observe substantial performance improvements when example test cases are included in the prompt, leading to higher Pass@1 scores and enhanced code coverage, particularly with more advanced LLMs.

Multi‐objective optimization is increasingly vital in complex circuit sizing, where traditional methods fail due to extensive design variables. This study focused on reducing the simulation counts, which are crucial for saving time, by optimizing the initial population selection in evolutionary algorithms. We investigated the impact of different sampling methods‐Latin hypercube, Sobol, and Halton‐on the efficiency of multi‐objective optimization based on differential evolution and Bayesian inference (MODEBI), a leading algorithm in circuit optimization. The experiments were conducted in two practical use cases of different complexities, low‐dropout voltage regulators (LDOs) with eight and, respectively, 27 design variables. We statistically analyzed the generated initial population sets for each sampling method and circuit. The results indicate that the Latin hypercube and Sobol significantly improve the initial population quality, leading to faster and more efficient optimization processes. This study highlights the importance of strategic initial population selection and its potential for streamlined circuit design optimization.

Component obsolescence and supply-chain disruptions increasingly force engineers to spend significant time manually searching and comparing PDF datasheets to identify compatible replacement parts. We propose an AI-powered datasheet assistant based on a Retrieval-Augmented Generation (RAG) pipeline that automatically processes datasheets to accelerate component identification and matching. The core contribution is a summary-driven retrieval mechanism: a Large Language Model (LLM) generates a structured semantic summary of an input datasheet, and the vector embedding of this summary is used to retrieve semantically similar components from a reference database. The system also supports natural language question answering and structured component comparison. Its architecture separates scalable text-only reference indexing from more expensive query-time summarization and reranking. Validation includes a controlled synthetic benchmark and a pilot-scale real-world evaluation on 18 publicly listed microcontroller datasheets grouped into six engineering families. The synthetic benchmark is used to assess pipeline behavior under controlled conditions, while the real-world evaluation measures performance on heterogeneous manufacturer datasheets. In the real-world evaluation, structured summaries generated with Claude Sonnet 4.5 combined with cross-encoder reranking achieved a 72.2% Family Retrieval Rate at $k=1$ (13/18; Wilson 95% CI: 49.1–87.5%). Additional experiments with local LLM summaries indicate that retrieval performance depends strongly on summary quality and model capability, with lightweight local summarizers producing lower first-candidate retrieval performance in this setup. The analysis further reports confidence intervals, no-summary baselines, chunking sensitivity, and an Image Reference Rate metric used as a lexical reference proxy rather than a direct measure of visual grounding.

Modern audio production workflows often require significant manual effort during the initial session preparation phase, including track labeling, format standardization, and gain staging. This paper presents a rule-based and Machine Learning-assisted automation system designed to minimize the time required for these tasks in Digital Audio Workstations (DAWs). The system automatically detects and labels audio tracks, identifies and eliminates redundant fake stereo channels, merges double-tracked instruments into stereo pairs, standardizes sample rate and bit rate across all tracks, and applies initial gain staging using target loudness values derived from a Genetic Algorithm (GA)-based system, which optimizes gain levels for individual track types based on engineer preferences and instrument characteristics. By replacing manual setup processes with automated decision-making methods informed by Machine Learning (ML) and rule-based heuristics, the system reduces session preparation time by up to 70% in typical multitrack audio projects. The proposed approach highlights how practical automation, combined with lightweight Neural Network (NN) models, can optimize workflow efficiency in real-world music production environments.

Embedded physical artificial intelligence (AI) combines sensing, learned inference and physical action under resource and timing constraints. This focused review synthesizes 62 detailed primary-source records across seven workload discussions and eight operation groups into conditional hardware requirements. Six cross-paper comparisons yield five adaptation judgments and one conditional functional match; none validates concurrent physical sharing. The reviewed audio fast Fourier transform (FFT) engine supports maximum lengths of 512/1024/2048 points at 32/16/8 bits per real or imaginary component, whereas the radar engine reaches 4096 points using half-precision arithmetic. Further configuration-specific contrasts expose memory and scheduling tradeoffs. An analytical MCUNetV2 example reduces peak activation storage from 1372 to 172 kB with 10% more multiply–accumulate operations. Published physical inverter tests at 40 kHz report parallel/sequential calculation times of 50/400 ns with 0.7% current total harmonic distortion in both; the corresponding synthesized designs use 200/70 digital signal processing cells. These findings motivate joint selection of numerical format, storage, execution granularity and timing budgets. A quantitative requirements matrix, explicit compatibility criteria and a conceptual architecture connect the evidence to configurable arithmetic, banked storage, state management, arbitration and software interfaces, with RISC-V as an implementation target. The framework distinguishes reusable operations and designs from concurrent resource sharing and specifies the numerical, task-quality and timing tests required to validate proposed mappings.