Răzvan Stancu

Mr. Răzvan Stancu


Research Focus & Metrics

Academic Career Length

1Year (2026-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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19 May 2026
Verified
Conference Paper
Open access
Jaume AbellaJaume Abella
Jaume Abella
SASergi Alcaide
Sergi Alcaide
EREric Rufart
Eric Rufart
LKLeonidas Kosmidis
Leonidas Kosmidis
APAlexandru Puşcaşu
Alexandru Puşcaşu
CBCalin Bira
Calin Bira

1 September 2026
Verified
Conference Paper
Closed access
CCCatalin Bogdan Ciobanu
Catalin Bogdan Ciobanu
FCFrancesco Conti
Francesco Conti
CCCairo Caplan
Cairo Caplan
HSHolger Schmidt
Holger Schmidt
WEWolfgang Ecker
Wolfgang Ecker
IFIngo Feldner
Ingo Feldner

7 November 2026 in Electronics
Verified
Journal Article
Open access
PDF file
RSRăzvan Stancu
Răzvan Stancu
APAlina-Luiza Petcu
Alina-Luiza Petcu
CDCosmin Costin Dumitru
Cosmin Costin Dumitru
DZDavid Han Zhao
David Han Zhao
GNGeorgian Nicolae
Georgian Nicolae
Embedded physical artificial intelligence (AI) combines sensing, learned inference and physical action under resource and timing constraints. This focused review synthesizes 62 detailed primary-source records across seven workload discussions and eight operation groups into conditional hardware requirements. Six cross-paper comparisons yield five adaptation judgments and one conditional functional match; none validates concurrent physical sharing. The reviewed audio fast Fourier transform (FFT) engine supports maximum lengths of 512/1024/2048 points at 32/16/8 bits per real or imaginary component, whereas the radar engine reaches 4096 points using half-precision arithmetic. Further configuration-specific contrasts expose memory and scheduling tradeoffs. An analytical MCUNetV2 example reduces peak activation storage from 1372 to 172 kB with 10% more multiply–accumulate operations. Published physical inverter tests at 40 kHz report parallel/sequential calculation times of 50/400 ns with 0.7% current total harmonic distortion in both; the corresponding synthesized designs use 200/70 digital signal processing cells. These findings motivate joint selection of numerical format, storage, execution granularity and timing budgets. A quantitative requirements matrix, explicit compatibility criteria and a conceptual architecture connect the evidence to configurable arithmetic, banked storage, state management, arbitration and software interfaces, with RISC-V as an implementation target. The framework distinguishes reusable operations and designs from concurrent resource sharing and specifies the numerical, task-quality and timing tests required to validate proposed mappings.