We participated in Taiwan's National Intercollegiate Athletic Games (NIAG) in early May 2021, and formed a Sport Technology Team of more than 30 scholars, students, and engineers to provide novel systems and solutions that make the athletic games rich in sport technologies. Some of the features could be the first time shown to the Internet audience for large-scale athletic games. The technologies involved include table tennis ball trajectory and bounce distribution, badminton shuttlecock tracking and trajectory, augmented-reality enriched video streaming on social networks, real-time three-dimensional broadcasting with free view-angle, in-stadium video stream pushing by a private fifth-generation (5G) network with multiaccess edge computing, AI-based sport data analytics during live streaming, etc. All the technologies and applications are integrated in a novel technology-enhanced broadcasting system (TEBS) that is dedicated to sport events. This article introduces the respective technologies that we have developed, deployed, and demonstrated in the 2021 NIAG. We stress the layered architecture design and integration of the TEBS, as well as experimental results from real games in the smart stadium and swimming pool. We also discuss the technical challenges and our approaches to tackle them, as well as lessons learned.

A low complexity fast mode decision algorithm for H.264/AVC intra prediction that uses discrete cross differences (DCD) to reduce the unlikely candidate modes in the RDO calculation is proposed. By using horizontal and vertical differences in different locations, the directions of the edges can be precisely detected. Experimental results show that the proposed fast mode decision algorithm reduces the encoding time by about 56%, with negligible loss of video quality. To realize the proposed algorithm, a VLSI design, which is comprised of a cross difference unit and direction detection unit, is implemented for the mode pre-selection stage of intra prediction. The design is synthesized using UMC 0.18 mum CMOS technology and simulated with Verilog-XL. The operating frequency of the synthesized core can exceed 50 MHz.

In this paper, two improved classifiers based on the nearest feature line (NFL) are proposed for image classification, where the neighborhood feature line segment-I (NFLS-I) classifier uses the neighborhood of prototypes to select the better-fitted feature lines (FLs) and the neighborhood feature line segment-II (NFLS-II) classifier utilizes the neighborhood of the query sample to choose more-likely FLs. With better selection of FLs, these two classifiers can both improve the recognition performance and the computation problem. A large number of experiments on Soil-100 object database, Yale face database, FEI face database, AR face database, and Jochen triesch static hand posture database are performed to evaluate these two proposed classifiers. The experimental results demonstrate that the proposed NFLS-I and NFLS-II classifiers outperform the original NFL and some other improved NFL classifiers for object recognition, hand posture recognition, and face recognition.

In H.264/AVC intra frame coding, the rate-distortion optimization is employed to select the optimal coding mode to achieve the minimum rate-distortion cost. Due to a large number of combinations of coding modes, the computational burden becomes extremely high in intra prediction, hi this paper, we propose a fast, efficient but reliable vector based detection algorithm for H.264 intra frame coding system. The proposed algorithm effectively estimates the edge direction inside the block to narrow down the predictive modes to reduce the RDO calculations. Experimental results show that the proposed method can reduce the encoding time by about 60% with negligible coding loss.

In this paper, a combined kernel architecture for efficiently decoding the residual data in the H.264/AVC baseline decoder is proposed. The kernel architecture in the H.264/AVC decoder consists of context-based adaptive variable length code (CAVLC) decoder, inverse quantization (IQ), and inverse transforms (IT) units. Since the decoding speeds of these kernel units vary with data, traditional methods require data buffers between these units. The first proposed architecture efficiently combines CAVLC decoding and IQ procedures. The multiple 2-D transforms architecture is applied to all inverse transforms, including the 4times4 inverse integer transform, the 4times4 inverse Hadamard transform and the 2times2 inverse Hadamard transform, to attain fewer gate counts than those of existing transform designs. Simulation results show that the total number of gates is 14.1 k and the maximum operating frequency is 130 MHz. For real-time requirements, in the worst case, the proposed architectures can achieve the operation speed of the H.264/AVC decoder up to 4VGA@30 frames/sec in 4:2:0 format.