In this article, a dynamic charge storage mechanism is proposed for designing the p-GaN gate dynamic charge storage high-electron-mobility transistor (DCS-HEMT) with ultralow switching loss. The device features a p-doped DCS layer in AlGaN buffer. When the DCS-HEMT is turning off, the net negative charges in the DCS layer significantly contribute to the depletion of 2-D-electron-gas (2DEG) channel, leading to low turn-off loss (Eoff). During turn-on process, reduction of the negative charges amount could accelerate the formation of electrons at the 2DEG channel, which results in low turn-on loss (Eon). Verified by the calibrated simulation, total switching loss (ESW = Eoff +Eon) of the designed DCS-HEMT is 61% lower than that of the conventional p-GaN gate HEMT (C-HEMT). The improved performance makes the DCS-HEMT a competitive candidate for low switching loss power applications.

The reverse blocking p-type GaN (p-GaN) gate high electron mobility transistors with multi-column p-GaN/Schottky alternate-island drain (MPS-HEMTs) are proposed and experimentally demonstrated. The p-GaN/AlGaN junctions (P-islands) and Schottky-contacts (S-islands) are alternately located by the side of the drain electrode. Multiple columns of these alternate-islands are formed in the staggered pattern successively, which can regulate the distribution of current density in the forward conduction and facilitate the 3-dimensional expanding (3DE) effect of depletion regions under the reverse bias as revealed by simulations. The fabricated MPS-HEMTs exhibit the low on-set voltage ${V}_{\text {ON}}$ of 0.31 V benefiting from the S-islands, the high reverse breakdown voltage BV _R of -1092 V from the P-islands, and simultaneously a low specific on-resistance ${R}_{\text {ON.SP}}$ of 8.3 $\text{m}\Omega \cdot $ cm ² for ${L}_{\text {GD}}$ of 22 $\mu \text{m}$ . The high-performance MPS-HEMTs have shown a much-improved trade-off among ${V}_{\text {ON}}$ , BV _R , and ${R}_{\text {ON.SP}}$ , which indicates the proposed multi-column p-GaN/Schottky alternate-island drain structure to be promising in p-GaN power device platforms.

In this article, the degradation behavior and mechanism of GaN high-electron-mobility transistors (HEMTs) with p-type gate in the third quadrant under repetitive surge current stress are studied. The electrical properties of devices under various surge current conditions are investigated. It can be found that the turning point exists in the degradation trend of threshold voltage ( ${V}_{\text{TH}}$ ), gate leakage current ( ${I}_{\text{gss}}$ ), and OFF-state drain leakage current ( ${I}_{\text{dss}}$ ). The turning phenomenon is related to the peak value of the surge current ( ${I}_{\text{peak}}$ ) and the stress cycle. We propose that two competing mechanisms that take place on carrier transport paths cause the degradation behavior. When ${I}_{\text{peak}}$ is low, the electron trapping effect is the main degradation mechanism. As ${I}_{\text{peak}}$ exceeds a certain value, as the stress cycle increases, the hole trapping effect will be greatly enhanced and even cause the reversal of the degradation rate of ${V}_{\text{TH}}$ , ${I}_{\text{gss}}$ , and ${I}_{\text{dss}}$ . Furthermore, at higher ${I}_{\text{peak}}$ , new donor traps can be generated in the gate, causing the permanent and negative shift of ${V}_{\text{TH}}$ . Based on the simulation, further experiments, and ${V}_{\text{TH}}$ recovery characteristics, the competing mechanism is confirmed. These results provide deep insights and references for the reliable applications of GaN HEMTs.

In this paper, input capacitance ( C _ISS ) of p-GaN gate AlGaN/GaN power high-electron-mobility transistors (HEMTs) is systemically investigated. C _ISS includes gate-to-source capacitance ( C _GS ) and gate-to-drain capacitance ( C _GD ). In comparison with the normally-on HEMTs, it is found that the phenomenon of C _ISS variation is different in the commercial p-GaN gate HEMTs. The unique charge storage effect in the typical p-GaN layer is adopted and discussed to explain the variation of C _ISS and establish the underlying mechanism. Owing to the depletion of holes, net negative charges are induced in the p-GaN layer under an off-state drain bias. It is demonstrated that the negative charge storage makes significant contribution to the increase of C _GS before the two-dimensional-electron-gas channel under source-field-plate (SFP) pinches off. Due to the clamped electric field distributions at drain-side edge of the p-GaN layer, the charge storage stops changing C _GS after the SFP pinche-off. Additionally, the storage has a minor influence on the variation of C _GD . Verified by the experimentally calibrated TCAD simulation, this work reveals a novel mechanism of charge storage impact on C _ISS variation in p-GaN gate AlGaN/GaN power HEMTs, which is of benefit to the C _ISS related capacitance design and gate driver optimization of the devices.

An analytical model considering the buffer acceptor traps is presented in this paper to study the gate control capability in p-GaN gate AlGaN/GaN high-electron-mobility transistors (HEMTs). Through applying Gauss’ law from the buffer layer to the two-dimensional-electron-gas (2DEG) channel in the GaN channel layer, the contributions of buffer acceptor trap concentration (N _A) and energy level (E _T) are obtained for calculating the gate voltage (V _G) dependent 2DEG density (n _S) and threshold voltage (V _TH) performance. It is suggested that the deep E _T acceptor traps in the buffer layer are of great importance to the gate control capability. Plenty of the deep E _T acceptor traps could be ionized at the top region of the buffer layer. These ionized acceptor traps are negatively charged and electrostatically influence the 2DEG density, which is the role of deep E _T on gate control. Then, the n _S-V _G and V _TH characteristics of the devices could be significantly modulated by the N _A. Furthermore, the influence of the shallow E _T acceptor traps is not strong and could be ignored in the prediction of the n _S-V _G and V _TH distributions. This is due to the fact that few shallow E _T acceptor traps are ionized in the buffer layer. The analytical results are well supported by the calibrated TCAD simulation, revealing the impact mechanism of buffer acceptor traps on the device gate control capability and serving as more accurate guidance for designing the n _S-V _G and V _TH in p-GaN gate AlGaN/GaN HEMTs.

This letter experimentally demonstrates an integrated bidirectional protection structure to improve the p-GaN power HEMTs’ gate ESD reliability. The protection structure comprises an event-triggering p-GaN HEMT, a low-side resistor ${R}_{\text {L}}$ , and a high-side resistor ${R}_{\text {H}}$ . The critical parameters such as transmission line pulsing (TLP) failure current, trigger voltage ${V}_{\text {Trig}}$ and leakage current ${I}_{\text {leak}}$ are evaluated by TLP testing. It is validated that this protection structure can sustain a forward TLP failure current up to 1.42 A (equivalent human body model passing voltage ${V}_{\text {HBM}} \approx {2.13}$ kV) and a reverse TLP failure current up to 3.06 A ( ${V}_{\text {HBM}} \approx {4.59}$ kV) without sacrificing the protected device’s performance. In addition, it is verified that the TLP failure current can be adjusted by the event-triggering p-GaN HEMT’s active area and ${R}_{\text {H}}/{R}_{\text {L}}$ ratio.