Background: The smart grid communication network is constructed with three tiers namely, Home Area Networks (HANs), Neighborhood Area Networks (NANs) and Wide Area Networks (WANs). These networks function with various communication protocols like table protocol, on-demand protocol, Wi-Fi, Zigbee, Z-Wave, Wi-MAX, GSM, LTE, Cognitive Radio Networks. The network interconnection is heterogonous and all appliances have to communicate through the IP gateways. A large amount of data is collected from various sensors placed in different locations. The analytics on large data- “big data” is essential because these data were used to organize and plan an efficient control and management of the smart home including secured data exchange in different sectors. Objective: This paper investigates broadly on data rate, channel bandwidth, power consumption, and a coverage range of both wired and wireless communication technologies used in residential buildings. Besides, a literature survey on optimization algorithms with various constraints to manage home appliances through scheduling is included. The paper also discusses the communication standards along with security and privacy requirements for smart metering networks. Conclusion: Discussion on IEEE standards for both wired and wireless communication protocols. Gives direction to identify the suitable communication technique through mathematical model for computing the communication channel bandwidth. Comparison of various optimization algorithms with multiple constraints in HEMS to achieve the minimum electricity cost and user comfort (with and without Renewable Energy Sources). From the investigation on both wired and wireless networks, the wireless communication networks (Zig-Bee & Wi-Fi) are mostly preferred to use in HAN because of more reliability and low cost. Zigbee is the most appropriate technology used for data transmission between the individual appliances and smart meters. Wi-Fi is a suitable technology for controlling and monitoring appliances because of its high data rate.

The automobile sector is a promising avenue for enhancing energy security, economic opportunity, and air quality in India. Before penetrating a large number of electric vehicles (EV) into the power grid, a thorough investigation and assessment of significant parameters are required, as additional nonlinear and EV loads are linked to the decentralized market. Many automobile companies have already invested in electric vehicle research; hence, a detailed analysis on range anxiety and grid connectivity concerns are the important factors affecting the future of the electric vehicle industry. In this paper, the initial review is about the decentralized market in India and sustainable aspects of electric mobility based on the Indian context, as it is a developing nation with an enormous resource and scope for EV markets. With recent literature from the last three years, the substantial constraints observed in benefits and challenges are reviewed. The financial stability aspects and the incentives to overcome the barriers to EV adoption are briefly discussed. From the review, it has come to the limelight that infrastructure availability, technology, load demand, and consumer behaviour are all major obstacles in the electric vehicle ecosystem. For the overall design and study of the vehicle to grid (V2G) infrastructure, this paper also provides insight into the representation of electric vehicles in different energy-efficient models and their categorization while connecting to the grid. The methodology adopted for energy-efficient models includes lifecycle emissions, economy, smart charging, real-time optimization, aggregated EV resource modelling, and a support vector machine (SVM)-based method. This paper gives a positive impact on EV fleet integration and electric mobility in general, as it critically reviews the influential parameters and challenges. This classification depends on crucial parameters that are at the frontline of EV grid integration research. This review is a solution to enhance grid stability in regard to new EV models. With the advanced electric motors development and renewed battery technology models, longer-distance automobiles are now available on the market. This paper investigates the constraints of EV grid integration and analyzes different EV models to ease the grid stability for a decentralized market.

Renewable energy penetration in the global energy sector is in a state of steady growth. A major criterion imposed by the regulatory boards in the wake of electronic-driven power systems is frequency regulation capability. As more rooftop PV systems are under installation, the inertia response of the power utility system is descending. The PV systems are not equipped inherently with inertial or governor control for unseen frequency deviation scenarios. In the proposed method, inertial and droop frequency control is implemented by creating the necessary power reserve by the derated operation of the PV system. While, traditionally, PV systems operate in normal MPPT mode, a derated PV system follows a flexible power point tracking (FPPT) algorithm for creating virtual energy storage. The point of operation for the FPPT of the PV is determined by using a neural network block set available in MATLAB. For the verification of the controller, it is applied to a PV array in a modified IEEE-13 bus system modeled in the MATLAB/Simulink platform. The simulation results prove that when the proposed control is applied to the test network with renewable energy penetration, there is an improved system inertia response.

The Vedic Multiplier and the Reversible Logic Gates has Designed and implemented in the multiply and Accumulate Unit (MAC) and that is shown in this paper. A Vedic multiplier is designed by using Urdhava Triyagbhayam sutra and the adder design is done by using reversible logic gate. Reversible logics are also the fundamental requirement for the emerging field of Quantum computing. The Vedic multiplier is used for the multiplication unit so as to reduce partial products and to get high performance and lesser area. The reversible logic is used to get less power. The MAC is designed in Verilog HDL and the simulation is done in Modelsim, Xilinx 14.2 and synthesis is done in both RTL compiler using cadence as well as Xilinx. The chip design for the proposed MAC is also carried out.