In this paper, we designed a novel tunable terahertz (THz) absorber that has unique properties of graphene integrated within a dual-layer metasurface structure. The proposed absorber demonstrates excellent performance by achieving eight distinct absorption peaks from 3.9 THz to 9.73 THz with an average absorption efficiency of 99.3%. This is achieved through the tunable surface conductivity of graphene which enables dynamic modulation of resonant frequencies via chemical potential adjustment. The design includes a gold base layer for total reflection, gallium arsenide (GaAs) dielectric spacers for optimum impedance matching and graphene patches to introduce multi-band absorption modes. Simulation results show the absorber's tunability, polarization insensitivity and angular stability which makes it highly adaptable for applications in medical diagnostics, material characterization, security screening and terahertz sensing. The proposed absorber's innovative architecture and simple design offers a versatile solution for the evolving demands of modern terahertz technologies.

Supply fluctuation is one of the most significant factors that cause jitter in high-speed I/O links. The traditional SPICE simulation or measuring method for power supply induced jitter is quite time-consuming and draining on resources. The I/O buffer information specification (IBIS) model is a popular standard for electronic behavioral specifications of digital integrated circuit I/O characteristics. Analytic jitter transfer functions for supply fluctuations are derived by solving two-order differential equations based on IBIS current versus voltage characteristics and pin package parameters. Then, the total time interval error induced by power and ground noise is obtained in both frequency domain and time domain. The method is validated by comparing the analytic calculation results with HSPICE simulated results for a DDR4 output buffer.

A fast and accurate statistical eye diagram estimation method for high-speed nonlinear links is proposed in this article. Probability density functions (PDFs) of output responses are derived based on multiple edge responses (MERs). According to the property that the influence of nonlinearity will not propagate for a long time in high-speed links, a new scheme for calculating the PDFs of responses is presented, in which the convolution process is divided into nonlinear section, transition section, and linear section. Convolutions via high-order of MERs are only used for the nonlinear section, low-order of MERs are used for the transition section, and double edge responses are used for the linear section. The new scheme can drastically reduce the amount of computation. The proposed method is verified by comparing the probability density distributions of the statistical eye diagram, the bathtub curves, and the simulation time with that of the traditional total MER-based statistical eye diagram. Results show that the simulation speed of the proposed method has been improved by more than ten times, and the accuracy is almost the same as the traditional statistical eye diagram for nonlinear links. This method provides an efficient and accurate solution for estimating the statistical and BER eye diagrams for serious nonlinear links.

For high-speed coding buses, it is a great challenge to evaluate the eye diagram accurately. Assuming that all data bits are independent and have uniform probabilities as previous estimation methods have done is not valid. In this paper, a new statistical method is proposed to estimate the worst-case eye diagrams and bit-error-rate (BER) eye diagrams for coding buses. The probability distribution of coded bus bit vectors is modeled based on the coding rule constraints. Then, actual worst pattern and eye diagram calculation is derived based on bus bit transition probabilities and double-edge responses. In order to validate the method, a parallel link with data bus inversion coding and 4b/6b coding is simulated, respectively. Worst case eye diagrams and BER eye diagrams are calculated and compared with that of no consideration of coding. Compared to the traditional statistical methods, this method eliminates the error due to the invalid assumption and provides more accurate results for designers.

There is a recognized need to evaluate the performance of high-speed links accurately and quickly with increasing clock frequency. To evaluate the performance of the systems, the transient simulation method and the fast time-domain simulation method are adopted. Unfortunately, neither method can guarantee both the efficiency and accuracy of the results at the same time. In this article, a modeling method that can overcome the shortcomings of both the transient simulation method and the fast time-domain simulation method is proposed for obtaining responses of high-speed links based on bidirectional long short-term memory (Bi-LSTM). Here, the pulse response and response of a certain number of bits are first simulated or measured, which are used to determine training datasets. Then, the Bi-LSTM-based model uses the generated training datasets to build a precise model. Next, the developed model predicts the response of the high-speed link. Compared to the transient simulation method and fast time-domain simulation method, the results show that the proposed method can consider both accuracy and efficiency. In addition, 33 simulation experiments are performed to demonstrate the robustness of the proposed method. Finally, the accuracy of the proposed method is validated by comparing the measured and predicted results of the high-speed links with different nonlinearities.

This article proposes an optimization algorithm using the Hessian minimization method, based on the Newton iteration, to evaluate the effectiveness of the placement of multiple decoupling capacitors on a power/ground plane pair. The exact effective decoupling regions are obtained using the Newton iteration method for each decoupling capacitor. The impedance of the IC port is lower than the target impedance no matter where the decoupling capacitor is placed in this region. To optimize specific capacitor placements in this region, the Newton iteration, based on the Hessian matrix, is used to determine the location where the impedance of the IC port is minimized at the antiresonant frequency of the plane pair. This placement optimization algorithm allows for a decoupling design method that can also be applied to a PDN with multiple decoupling capacitors for multiple IC ports. Compared with the method of random selection from within the effective decoupling area, the method proposed here requires fewer decoupling capacitors and less computational time.