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Dr. Minh-Khai Nguyen
Department of Electrical and Computer Engineering, Wayne State University, Detroit, MI 48202, USA

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Research Keywords & Expertise

0 Power Electronics
0 impedance-source converters
0 Multilevel inverters
0 PWM strategies
0 Power converters for renewable energy systems and electric vehicles

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Journal article
Published: 30 June 2021 in Energies
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A new modulation strategy has been introduced in this paper in order to enhance the boost factor for the three-level quasi-switched boost T-type inverter (3L-qSBT2I). Under this approach, the component rating of power devices is significantly decreased. Moreover, the use of a larger boost factor produces a smaller shoot-through current. This benefit leads to reducing the conduction loss significantly. Furthermore, the neutral voltage unbalance is also considered. The duty cycle of two active switches of a quasi-switched boost (qSB) network is redetermined based on actual capacitor voltages to recovery balance condition. Noted that the boost factor will not be affected by the proposed capacitor voltage balance strategy. The proposed method is taken into account to be compared with other previous studies. The operation principle and overall control strategy for this configuration are also detailed. The simulation and experiment are implemented with the help of PSIM software and laboratory prototype to demonstrate the accuracy of this strategy.

ACS Style

Duc-Tri Do; Vinh-Thanh Tran; Minh-Khai Nguyen. Enhanced Boost Factor for Three-Level Quasi-Switched Boost T-Type Inverter. Energies 2021, 14, 3920 .

AMA Style

Duc-Tri Do, Vinh-Thanh Tran, Minh-Khai Nguyen. Enhanced Boost Factor for Three-Level Quasi-Switched Boost T-Type Inverter. Energies. 2021; 14 (13):3920.

Chicago/Turabian Style

Duc-Tri Do; Vinh-Thanh Tran; Minh-Khai Nguyen. 2021. "Enhanced Boost Factor for Three-Level Quasi-Switched Boost T-Type Inverter." Energies 14, no. 13: 3920.

Review
Published: 20 June 2021 in Electronics
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This paper presents a comprehensive review based on the features and drawbacks of the quasi-switched boost inverter (qSBI) topologies. The qSBI derived configurations are well suitable for low power applications due to their reduced number of components. This work focuses on the topological review of qSBI derived topologies and serves as a reference for further derivation and research on the selection of suitable topology for the specific renewable energy applications, particularly based on the photovoltaic (PV) converters.

ACS Style

Jg Barath; Ayyasamy Soundarrajan; Serhii Stepenko; Oleksandr Husev; Dmitri Vinnikov; Minh-Khai Nguyen. Topological Review of Quasi-Switched Boost Inverters. Electronics 2021, 10, 1485 .

AMA Style

Jg Barath, Ayyasamy Soundarrajan, Serhii Stepenko, Oleksandr Husev, Dmitri Vinnikov, Minh-Khai Nguyen. Topological Review of Quasi-Switched Boost Inverters. Electronics. 2021; 10 (12):1485.

Chicago/Turabian Style

Jg Barath; Ayyasamy Soundarrajan; Serhii Stepenko; Oleksandr Husev; Dmitri Vinnikov; Minh-Khai Nguyen. 2021. "Topological Review of Quasi-Switched Boost Inverters." Electronics 10, no. 12: 1485.

Journal article
Published: 05 April 2021 in IEEE Transactions on Power Electronics
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This paper introduces a space vector control method for the three-level quasi-switched boost T-type inverter (3L-qSBT2I) which provides some benefits such as good output voltage quality, high voltage gain, and low voltage stress on power devices. By applying corresponding P-type or N-type small vectors in the switching sequence, the neutral-point voltage unbalance problem can be solved easily. The advantage of this modulation solution is that it does not require any extra calculations. The upper-shoot-through (UST) and lower-shoot-through (LST) states are utilized instead of full-shoot-through (FST), which is usually used in traditional single-stage three-level impedance source inverter, to ensure the boost capability of the inverter. These states are inserted into small vectors in order not to affect the output line-to-line voltage. Some investigations about voltage gain, diode, and switch voltage stress have been conducted to demonstrate the effectiveness of the proposed method. The experimental results are also presented to validate the accuracy of the proposed modulation method. The proposed approach has resulted in an efficiency rise by 2% as compared to the conventional PWM scheme.

ACS Style

Vinh-Thanh Tran; Minh-Khai Nguyen; Duc-Tri Do; Dmitri Vinnikov. An SVM Scheme for Three-Level Quasi-Switched Boost T-Type Inverter With Enhanced Voltage Gain and Capacitor Voltage Balance. IEEE Transactions on Power Electronics 2021, 36, 11499 -11508.

AMA Style

Vinh-Thanh Tran, Minh-Khai Nguyen, Duc-Tri Do, Dmitri Vinnikov. An SVM Scheme for Three-Level Quasi-Switched Boost T-Type Inverter With Enhanced Voltage Gain and Capacitor Voltage Balance. IEEE Transactions on Power Electronics. 2021; 36 (10):11499-11508.

Chicago/Turabian Style

Vinh-Thanh Tran; Minh-Khai Nguyen; Duc-Tri Do; Dmitri Vinnikov. 2021. "An SVM Scheme for Three-Level Quasi-Switched Boost T-Type Inverter With Enhanced Voltage Gain and Capacitor Voltage Balance." IEEE Transactions on Power Electronics 36, no. 10: 11499-11508.

Journal article
Published: 22 September 2020 in IEEE Access
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The space vector modulation (SVM) method using only rotating vectors is very effective to suppress the common-mode voltage (CMV) for matrix converters (MCs). However, the effect of the input filter on the input power factor (IPF) has not been fully investigated when using this method. This study investigated the effect of the input filter on the displacement angle and proposes an IPF compensation strategy for the zero CMV-SVM method in MCs. The proposed strategy analyzes the duty cycles of rotating vectors under the IPF-compensation condition. Through this analysis, the proposed strategy adjusts the zero vector by using a set of three counterclockwise-rotating vectors or three clockwise-rotating vectors to make all the duty cycles non-negative, ensuring that the zero CMV-SVM method can be applied to compensate the IPF for the MCs. This study also determines the condition to achieve unity IPF for the main power source and the maximum allowable IPF if the above condition is not met. Finally, experimental results are provided to validate the theoretical study.

ACS Style

Huu-Nhan Nguyen; Minh-Khai Nguyen; Van-Quang-Binh Ngo; Tan-Tai Tran; Joon-Ho Choi; Young-Cheol Lim. Input Power Factor Compensation Strategy for Zero CMV-SVM Method in Matrix Converters. IEEE Access 2020, 8, 175805 -175814.

AMA Style

Huu-Nhan Nguyen, Minh-Khai Nguyen, Van-Quang-Binh Ngo, Tan-Tai Tran, Joon-Ho Choi, Young-Cheol Lim. Input Power Factor Compensation Strategy for Zero CMV-SVM Method in Matrix Converters. IEEE Access. 2020; 8 (99):175805-175814.

Chicago/Turabian Style

Huu-Nhan Nguyen; Minh-Khai Nguyen; Van-Quang-Binh Ngo; Tan-Tai Tran; Joon-Ho Choi; Young-Cheol Lim. 2020. "Input Power Factor Compensation Strategy for Zero CMV-SVM Method in Matrix Converters." IEEE Access 8, no. 99: 175805-175814.

Journal article
Published: 10 September 2020 in IEEE Access
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This paper introduces a new three-phase two-level inverter based on the switched-capacitor voltage multiplier. By adding a voltage multiplier network at the DC side of the traditional three-phase inverter topology, the DC-link voltage of the introduced inverter is stepped up to triple of the input voltage. Compared to the existing solutions, the common-mode voltage of the introduced topology is kept constant. Moreover, the voltage stress across additional semiconductor components is the same as one-third of DC-link voltage. Operating principles, mathematical analysis, circuit analysis, and pulse-width modulation (PWM) method based on the Boolean logic function for introduced inverter are presented. A comparison of the introduced inverter with other inverter topologies is also reported. The simulation results are shown to verify the introduced three-phase triple voltage boost inverter. Besides that, a laboratory-built prototype is developed based on a DSP F280049C microcontroller and the corresponding experimental tests are provided to prove the introduced inverter.

ACS Style

Tan-Tai Tran; Minh-Khai Nguyen; Van-Quang-Binh Ngo; Huu-Nhan Nguyen; Truong-Duy Duong; Young-Cheol Lim; Joon-Ho Choi. A Three-Phase Constant Common-Mode Voltage Inverter With Triple Voltage Boost for Transformerless Photovoltaic System. IEEE Access 2020, 8, 166692 -166702.

AMA Style

Tan-Tai Tran, Minh-Khai Nguyen, Van-Quang-Binh Ngo, Huu-Nhan Nguyen, Truong-Duy Duong, Young-Cheol Lim, Joon-Ho Choi. A Three-Phase Constant Common-Mode Voltage Inverter With Triple Voltage Boost for Transformerless Photovoltaic System. IEEE Access. 2020; 8 (99):166692-166702.

Chicago/Turabian Style

Tan-Tai Tran; Minh-Khai Nguyen; Van-Quang-Binh Ngo; Huu-Nhan Nguyen; Truong-Duy Duong; Young-Cheol Lim; Joon-Ho Choi. 2020. "A Three-Phase Constant Common-Mode Voltage Inverter With Triple Voltage Boost for Transformerless Photovoltaic System." IEEE Access 8, no. 99: 166692-166702.

Journal article
Published: 20 July 2020 in Energies
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In recent years, the three-level T-Type inverter has been considered the best choice for many low and medium power applications. Nevertheless, this topology is known as a buck converter. Therefore, in this paper, a new topology incorporating the dc-link type quasi-switched boost network with the traditional three-level T-type inverter is proposed to overcome the limit of traditional three-level T-Type inverter. The space vector pulse width modulation scheme is considered to control this topology, which provides some benefits such as enhancing modulation index and reducing the magnitude of common-mode voltage. For this scheme, the zero, medium, and large vectors are utilized to generate the output voltage. The shoot-through state which is adopted by turning on all power switches of inverter leg is inserted into zero vector to boost the dc-link voltage. As a result, there is no distortion at the output waveform. The control signal of intermediate network power switches is also detailed to improve the boost factor and voltage gain. As a result, the voltage stress on power devices like capacitors, diodes, and switches is decreased significantly. To demonstrate the outstanding of proposed structure and its control strategy, some comparisons between the proposed method and other ones are performed. Simulation and experimental prototype results are conducted to verify the accuracy of the theory and effectiveness of the inverter.

ACS Style

Vinh-Thanh Tran; Duc-Tri Do; Van-Dung Do; Minh-Khai Nguyen. A Three-Level DC-Link Quasi-Switch Boost T-Type Inverter with Voltage Stress Reduction. Energies 2020, 13, 3727 .

AMA Style

Vinh-Thanh Tran, Duc-Tri Do, Van-Dung Do, Minh-Khai Nguyen. A Three-Level DC-Link Quasi-Switch Boost T-Type Inverter with Voltage Stress Reduction. Energies. 2020; 13 (14):3727.

Chicago/Turabian Style

Vinh-Thanh Tran; Duc-Tri Do; Van-Dung Do; Minh-Khai Nguyen. 2020. "A Three-Level DC-Link Quasi-Switch Boost T-Type Inverter with Voltage Stress Reduction." Energies 13, no. 14: 3727.

Editorial
Published: 16 April 2020 in Electronics
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In recent years, power converters have played an important role in power electronics technology for different applications, such as renewable energy systems, electric vehicles, pulsed power generation, and biomedical

ACS Style

Minh-Khai Nguyen. Power Converters in Power Electronics: Current Research Trends. Electronics 2020, 9, 654 .

AMA Style

Minh-Khai Nguyen. Power Converters in Power Electronics: Current Research Trends. Electronics. 2020; 9 (4):654.

Chicago/Turabian Style

Minh-Khai Nguyen. 2020. "Power Converters in Power Electronics: Current Research Trends." Electronics 9, no. 4: 654.

Journal article
Published: 16 March 2020 in IEEE Access
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ACS Style

Minh-Khai Nguyen; Truong-Duy Duong; Young-Cheol Lim; Joon-Ho Choi; Don Mahinda Vilathgamuwa; Geoffrey R. Walker. DC-Link Quasi-Switched Boost Inverter With Improved PWM Strategy and its Comparative Evaluation. IEEE Access 2020, 8, 53857 -53867.

AMA Style

Minh-Khai Nguyen, Truong-Duy Duong, Young-Cheol Lim, Joon-Ho Choi, Don Mahinda Vilathgamuwa, Geoffrey R. Walker. DC-Link Quasi-Switched Boost Inverter With Improved PWM Strategy and its Comparative Evaluation. IEEE Access. 2020; 8 ():53857-53867.

Chicago/Turabian Style

Minh-Khai Nguyen; Truong-Duy Duong; Young-Cheol Lim; Joon-Ho Choi; Don Mahinda Vilathgamuwa; Geoffrey R. Walker. 2020. "DC-Link Quasi-Switched Boost Inverter With Improved PWM Strategy and its Comparative Evaluation." IEEE Access 8, no. : 53857-53867.

Journal article
Published: 01 January 2020 in Electronics
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In this paper, the effect of common-mode voltage generated in the three-level quasi-switched boost T-type inverter is minimized by applying the proposed space-vector modulation technique, which uses only medium vectors and zero vector to synthesize the reference vector. The switching sequence is selected smoothly for inserting the shoot-through state for the inverter branch. The shoot-through vector is added within the zero vector in order to not affect the active vectors as well as the output voltage. In addition, the shoot-through control signal of active switches of the impedance network is generated to ensure that its phase is shifted 90 degrees compared to shoot through the signal of the inverter leg, which provides an improvement in reducing the inductor current ripple and enhancing the voltage gain. The effectiveness of the proposed method is verified through simulation and experimental results. In addition, the superiority of the proposed scheme is demonstrated by comparing it to the conventional pulse-width modulation technique.

ACS Style

Duc-Tri Do; Minh-Khai Nguyen; Van-Thuyen Ngo; Thanh-Hai Quach; Vinh-Thanh Tran. Common Mode Voltage Elimination for Quasi-Switch Boost T-Type Inverter Based on SVM Technique. Electronics 2020, 9, 76 .

AMA Style

Duc-Tri Do, Minh-Khai Nguyen, Van-Thuyen Ngo, Thanh-Hai Quach, Vinh-Thanh Tran. Common Mode Voltage Elimination for Quasi-Switch Boost T-Type Inverter Based on SVM Technique. Electronics. 2020; 9 (1):76.

Chicago/Turabian Style

Duc-Tri Do; Minh-Khai Nguyen; Van-Thuyen Ngo; Thanh-Hai Quach; Vinh-Thanh Tran. 2020. "Common Mode Voltage Elimination for Quasi-Switch Boost T-Type Inverter Based on SVM Technique." Electronics 9, no. 1: 76.

Journal article
Published: 01 January 2020 in Electronics
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In practice, the input filter is an important component in matrix converter (MC) systems for removing high harmonic components from input currents. Due to the input filter, the input power factor (IPF) at the main power supply does not always achieve unity. To investigate the behavior of the IPF, this paper analyzes the IPF compensation capacity of MCs with an LC input filter based on space vector theory and the conservation of energy law. The study shows that the range of voltage transfer ratio (VTR) to achieve unity IPF depends strongly on the quality factor, which is determined by the system parameters. If the quality factor is greater than 0.375, the MC can never achieve unity IPF for the whole range of VTR. If the quality factor is lower than 0.375, the MC can only achieve unity IPF for a certain range of VTR, except at a very low or very high VTR. Experimental results are provided to confirm the correctness of the study.

ACS Style

Huu-Nhan Nguyen; Minh-Khai Nguyen; Truong-Duy Duong; Tan-Tai Tran; Young-Cheol Lim; Joon-Ho Choi. A Study on Input Power Factor Compensation Capability of Matrix Converters. Electronics 2020, 9, 82 .

AMA Style

Huu-Nhan Nguyen, Minh-Khai Nguyen, Truong-Duy Duong, Tan-Tai Tran, Young-Cheol Lim, Joon-Ho Choi. A Study on Input Power Factor Compensation Capability of Matrix Converters. Electronics. 2020; 9 (1):82.

Chicago/Turabian Style

Huu-Nhan Nguyen; Minh-Khai Nguyen; Truong-Duy Duong; Tan-Tai Tran; Young-Cheol Lim; Joon-Ho Choi. 2020. "A Study on Input Power Factor Compensation Capability of Matrix Converters." Electronics 9, no. 1: 82.

Journal article
Published: 28 November 2019 in Electronics
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High-voltage gain conversion is necessary for several applications, especially for low voltage renewable source applications. In order to achieve a high-voltage gain, the presented paper proposes a class of transformerless DC-DC converters based on three switched-capacitor networks. The proposed converters have the following characteristics: reduced voltage stress on the capacitors and power devices; obtained high voltage gain with small duty cycle; and reduced conduction losses in the power switches. To verify the operation principle of the proposed converters, the detailed analysis in different conditions of the proposed converters and a comparison considering existing topologies are also discussed in the paper. Moreover, the parameter selection and controller design for the converters are determined. Finally, to reconfirm the theoretical analysis, both the simulation and experimental results taken from a 400 W prototype operating at 60 kHz are given.

ACS Style

Truong-Duy Duong; Minh-Khai Nguyen; Tan-Tai Tran; Young-Cheol Lim; Joon-Ho Choi. Transformerless High Step-Up DC-DC Converters with Switched-Capacitor Network. Electronics 2019, 8, 1420 .

AMA Style

Truong-Duy Duong, Minh-Khai Nguyen, Tan-Tai Tran, Young-Cheol Lim, Joon-Ho Choi. Transformerless High Step-Up DC-DC Converters with Switched-Capacitor Network. Electronics. 2019; 8 (12):1420.

Chicago/Turabian Style

Truong-Duy Duong; Minh-Khai Nguyen; Tan-Tai Tran; Young-Cheol Lim; Joon-Ho Choi. 2019. "Transformerless High Step-Up DC-DC Converters with Switched-Capacitor Network." Electronics 8, no. 12: 1420.

Research article
Published: 21 October 2019 in IET Power Electronics
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In this study, an improved pulse width modulation (PWM) scheme was proposed for an active quasi-Z source inverter (AqZSI). Compared to the quasi-Z-source inverter (qZSI), the AqZSI with improved PWM strategy can operate in a wide range of input voltage with higher efficiency. Furthermore, the AqZSI can operate with a higher modulation index, a lower inductor current stress, and a reduced shoot-through current. A procedure flowchart is presented for the optimal selection of the shoot-through duty cycle, the switching ratio of the additional switch, and the modulation index for AqZSI. Moreover, some comparative results between the AqZSI, qZSI and conventional two-stage inverter with a boost DC–DC converter are shown in detail. Finally, 1.2 kVA SiC-based three-phase inverter prototypes are built to verify the agreement between theory and measurement.

ACS Style

Truong‐Duy Duong; Minh‐Khai Nguyen; Young‐Cheol Lim; Joon‐Ho Choi; D. Mahinda Vilathgamuwa. SiC‐based active quasi‐Z‐source inverter with improved PWM control strategy. IET Power Electronics 2019, 12, 3810 -3821.

AMA Style

Truong‐Duy Duong, Minh‐Khai Nguyen, Young‐Cheol Lim, Joon‐Ho Choi, D. Mahinda Vilathgamuwa. SiC‐based active quasi‐Z‐source inverter with improved PWM control strategy. IET Power Electronics. 2019; 12 (14):3810-3821.

Chicago/Turabian Style

Truong‐Duy Duong; Minh‐Khai Nguyen; Young‐Cheol Lim; Joon‐Ho Choi; D. Mahinda Vilathgamuwa. 2019. "SiC‐based active quasi‐Z‐source inverter with improved PWM control strategy." IET Power Electronics 12, no. 14: 3810-3821.

Journal article
Published: 23 July 2019 in IEEE Access
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In this paper, a modified three-phase two-level voltage source inverter is proposed. By combining the conventional three-phase H-bridge inverter with a switched-capacitor-voltage-doubler network, the DC-link voltage of the proposed inverter is double with respect to the input DC voltage. As a result, the output voltage of the proposed inverter can be higher than the input DC voltage. Furthermore, a common-mode voltage (CMV) of the proposed inverter can be reduced through controlling the two additional switches based on the space vector pulse-width modulation. Compared to the existing modulations and topologies, the variation in CMV can only be up to 16.6% of DC-link voltage. Furthermore, the voltage stress across additional switches and diodes is equal to half of DC-link voltage. Mathematical analysis, operating principles, and comparison of the proposed three-phase two-level voltage source inverter with the conventional three-phase voltage source inverters are presented. The simulation results based on PLECS software verify a good performance of the proposed inverter. Finally, a laboratory prototype based on a TMS320F280049 DSP is developed and experimental tests are carried out to validate the effectiveness of the proposed three-phase inverter topology

ACS Style

Tan-Tai Tran; Minh-Khai Nguyen; Truong-Duy Duong; Joon-Ho Choi; Young-Cheol Lim; Firuz Zare. A Switched-Capacitor-Voltage-Doubler Based Boost Inverter for Common-Mode Voltage Reduction. IEEE Access 2019, 7, 98618 -98629.

AMA Style

Tan-Tai Tran, Minh-Khai Nguyen, Truong-Duy Duong, Joon-Ho Choi, Young-Cheol Lim, Firuz Zare. A Switched-Capacitor-Voltage-Doubler Based Boost Inverter for Common-Mode Voltage Reduction. IEEE Access. 2019; 7 (99):98618-98629.

Chicago/Turabian Style

Tan-Tai Tran; Minh-Khai Nguyen; Truong-Duy Duong; Joon-Ho Choi; Young-Cheol Lim; Firuz Zare. 2019. "A Switched-Capacitor-Voltage-Doubler Based Boost Inverter for Common-Mode Voltage Reduction." IEEE Access 7, no. 99: 98618-98629.

Journal article
Published: 10 July 2019 in IEEE Journal of Emerging and Selected Topics in Power Electronics
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In this paper, a single-stage active impedance source three-phase T-type inverter is proposed with a reduced component count. Besides the inherent features of the three-level impedancesource inverters -shoot-through (ST) immunity, single-stage power conversion, and continuous input current, the proposed inverter has additional advantages such as increased voltage gain, reduced passive element count, and low voltage stress on devices. Furthermore, the self-balance capacitor voltage capability is the other feature of the proposed inverter. The steady-state analysis, operating principles, and parameter selection guidelines are presented in detail for the proposed inverter. PWM techniques for the proposed inverter including the sinusoidal PWM method and modified space-vector modulation scheme for common-mode voltage reduction are also presented. A comprehensive comparison between the proposed inverter and other three-level impedance-source inverters are shown. The proposed inverter has been validated using the PSIM simulation software and a laboratory prototype is constructed to verify the performance of the proposed inverter.

ACS Style

Minh-Khai Nguyen; Tan-Tai Tran; Firuz Zare. An Active Impedance-Source Three-Level T-Type Inverter With Reduced Device Count. IEEE Journal of Emerging and Selected Topics in Power Electronics 2019, 8, 2966 -2976.

AMA Style

Minh-Khai Nguyen, Tan-Tai Tran, Firuz Zare. An Active Impedance-Source Three-Level T-Type Inverter With Reduced Device Count. IEEE Journal of Emerging and Selected Topics in Power Electronics. 2019; 8 (3):2966-2976.

Chicago/Turabian Style

Minh-Khai Nguyen; Tan-Tai Tran; Firuz Zare. 2019. "An Active Impedance-Source Three-Level T-Type Inverter With Reduced Device Count." IEEE Journal of Emerging and Selected Topics in Power Electronics 8, no. 3: 2966-2976.

Conference paper
Published: 01 July 2019 in 2019 International Conference on System Science and Engineering (ICSSE)
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This paper presents a three-phase three-level quasi-Z-source inverter (qZSI) topology that can be operated in normal and fault tolerant operation modes. The presented structure is a combination of two symmetrical quasi-Z source networks and T-type inverter. The proposed topology has characterized by their semiconductor fault tolerance capability. This feature is only obtained by additional extra phase legs. In addition, the qZSI overcomes the issues of shoot-through (ST) mode and operating in normal and failure mode. The effectiveness of proposed inverter topology and control methods is validated by the simulation results.

ACS Style

Duc-Tri Do; Minh-Khai Nguyen; Thanh-Hai Quach; Van-Nho Nguyen; Thanh-Phuong Nguyen; Vinh-Thanh Tran. A Quasi-Z-source T-Type Inverter with Fault-Tolerant Capability. 2019 International Conference on System Science and Engineering (ICSSE) 2019, 37 -40.

AMA Style

Duc-Tri Do, Minh-Khai Nguyen, Thanh-Hai Quach, Van-Nho Nguyen, Thanh-Phuong Nguyen, Vinh-Thanh Tran. A Quasi-Z-source T-Type Inverter with Fault-Tolerant Capability. 2019 International Conference on System Science and Engineering (ICSSE). 2019; ():37-40.

Chicago/Turabian Style

Duc-Tri Do; Minh-Khai Nguyen; Thanh-Hai Quach; Van-Nho Nguyen; Thanh-Phuong Nguyen; Vinh-Thanh Tran. 2019. "A Quasi-Z-source T-Type Inverter with Fault-Tolerant Capability." 2019 International Conference on System Science and Engineering (ICSSE) , no. : 37-40.

Conference paper
Published: 01 July 2019 in 2019 International Conference on System Science and Engineering (ICSSE)
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In this paper, a new pulse width modulation (PWM) scheme for three-level T-type inverter is proposed to reduce switching loss of the inverter. The proposed modulation technique is based on the offset function being 3 rd harmonic voltage. The control voltage of phase, which has largest absolute value of load current, moves into the top or bottom of the carriers to have no switching in this phase. Therefore, the switching loss of the inverter is reduced. The switching loss of the inverter with the proposed PWM method is 33% lower compared to the conventional sinusoidal PWM method. The theoretical analysis is verified by simulation and experimental results.

ACS Style

Vinh-Thanh Tran; Thanh-Hai Quach; Duc-Tri Do; Minh-Khai Nguyen; My-Ha Le; Ngoc-Anh Truong. A Novel Offset Function for Three-Level T-Type Inverter to Reduce Switching Loss. 2019 International Conference on System Science and Engineering (ICSSE) 2019, 41 -44.

AMA Style

Vinh-Thanh Tran, Thanh-Hai Quach, Duc-Tri Do, Minh-Khai Nguyen, My-Ha Le, Ngoc-Anh Truong. A Novel Offset Function for Three-Level T-Type Inverter to Reduce Switching Loss. 2019 International Conference on System Science and Engineering (ICSSE). 2019; ():41-44.

Chicago/Turabian Style

Vinh-Thanh Tran; Thanh-Hai Quach; Duc-Tri Do; Minh-Khai Nguyen; My-Ha Le; Ngoc-Anh Truong. 2019. "A Novel Offset Function for Three-Level T-Type Inverter to Reduce Switching Loss." 2019 International Conference on System Science and Engineering (ICSSE) , no. : 41-44.

Journal article
Published: 21 June 2019 in Electronics
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In this paper, a new pulse width modulation (PWM) scheme using an offset function to reduce switching loss in the five-level H-bridge T-type inverter (5L-HBT2I) is proposed. The proposed modulation technique is implemented with a third harmonic offset voltage function. A new control voltage, that is adding the offset voltage into the initial control, is shifted to the top or bottom position of the carrier, simultaneously—where the absolute value of its load current is high or medium in comparison to other phase load currents. Due to reducing the intersection between a control voltage and the carriers, the number of switch commutations of the inverter is reduced. As a result of reducing the number of commutation count with a high current at the non-switching position, the switching losses of the inverter are decreased. Analysis and comparison of switching losses on the two-level and three-level inverters, which are components of 5L-HBT2I are presented. The power loss analysis on the 5L-HBT2I is performed. The proposed technique implements the switching loss reduction strategy based on setting the operation of the two-level inverter in six-step mode. PSIM software is used to clarify the proposed technique. The simulation results show that the total switching losses of the proposed technique in 5L-HBT2I reduce in comparison to the conventional sine PWM technique. A prototype is built to validate the proposed scheme. Simulation and experimental results match the analysis.

ACS Style

Thanh-Hai Quach; Duc-Tri Do; Minh-Khai Nguyen. A PWM Scheme for Five-Level H-Bridge T-Type Inverter with Switching Loss Reduction. Electronics 2019, 8, 702 .

AMA Style

Thanh-Hai Quach, Duc-Tri Do, Minh-Khai Nguyen. A PWM Scheme for Five-Level H-Bridge T-Type Inverter with Switching Loss Reduction. Electronics. 2019; 8 (6):702.

Chicago/Turabian Style

Thanh-Hai Quach; Duc-Tri Do; Minh-Khai Nguyen. 2019. "A PWM Scheme for Five-Level H-Bridge T-Type Inverter with Switching Loss Reduction." Electronics 8, no. 6: 702.

Journal article
Published: 13 June 2019 in IEEE Journal of Emerging and Selected Topics in Power Electronics
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In this paper, a new optimal pulse-width modulation (PWM) scheme for a three-level quasi-switched boost T-type inverter (TL qSBT2I) under normal and failure modes is proposed. The proposed method reveals its semiconductor fault tolerance capability in open-circuit fault condition situations as described in the paper. The PWM control algorithm for the fault-tolerant qSBT2I is implemented by selecting appropriate values for the modulation index, shoot-through (ST) duty cycle and duty cycles of two additional switches. The steady-state analysis and operating principles of the fault-tolerant qSBT2I are presented. A laboratory prototype was built to verify the operating principles of the qSBT2I with the proposed modulation scheme before and after fault conditions.

ACS Style

Duc-Tri Do; Minh-Khai Nguyen; Thanh-Hai Quach; Vinh-Thanh Tran; Frede Blaabjerg; D. Mahinda Vilathgamuwa. A PWM Scheme for a Fault-Tolerant Three-Level Quasi-Switched Boost T-Type Inverter. IEEE Journal of Emerging and Selected Topics in Power Electronics 2019, 8, 3029 -3040.

AMA Style

Duc-Tri Do, Minh-Khai Nguyen, Thanh-Hai Quach, Vinh-Thanh Tran, Frede Blaabjerg, D. Mahinda Vilathgamuwa. A PWM Scheme for a Fault-Tolerant Three-Level Quasi-Switched Boost T-Type Inverter. IEEE Journal of Emerging and Selected Topics in Power Electronics. 2019; 8 (3):3029-3040.

Chicago/Turabian Style

Duc-Tri Do; Minh-Khai Nguyen; Thanh-Hai Quach; Vinh-Thanh Tran; Frede Blaabjerg; D. Mahinda Vilathgamuwa. 2019. "A PWM Scheme for a Fault-Tolerant Three-Level Quasi-Switched Boost T-Type Inverter." IEEE Journal of Emerging and Selected Topics in Power Electronics 8, no. 3: 3029-3040.

Conference paper
Published: 01 May 2019 in 2019 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019 - ECCE Asia)
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ACS Style

Truong-Duy Duong; Minh-Khai Nguyen; Young-Cheol Lim; Joon-Ho Choi; Don Mahinda Vilathgamuwa. A Comparison Between Quasi-Z-Source Inverter and Active Quasi-Z-Source Inverter. 2019 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019 - ECCE Asia) 2019, 1 .

AMA Style

Truong-Duy Duong, Minh-Khai Nguyen, Young-Cheol Lim, Joon-Ho Choi, Don Mahinda Vilathgamuwa. A Comparison Between Quasi-Z-Source Inverter and Active Quasi-Z-Source Inverter. 2019 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019 - ECCE Asia). 2019; ():1.

Chicago/Turabian Style

Truong-Duy Duong; Minh-Khai Nguyen; Young-Cheol Lim; Joon-Ho Choi; Don Mahinda Vilathgamuwa. 2019. "A Comparison Between Quasi-Z-Source Inverter and Active Quasi-Z-Source Inverter." 2019 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019 - ECCE Asia) , no. : 1.

Conference paper
Published: 01 May 2019 in 2019 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019 - ECCE Asia)
Reads 0
Downloads 0
ACS Style

Tan-Tai Tran; Joon-Ho Choi; Minh-Khai Nguyen; Young-Cheol Lim. A Novel Space Vector Modulation Strategy for Three-Phase Quasi Switched Boost Inverter. 2019 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019 - ECCE Asia) 2019, 1 .

AMA Style

Tan-Tai Tran, Joon-Ho Choi, Minh-Khai Nguyen, Young-Cheol Lim. A Novel Space Vector Modulation Strategy for Three-Phase Quasi Switched Boost Inverter. 2019 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019 - ECCE Asia). 2019; ():1.

Chicago/Turabian Style

Tan-Tai Tran; Joon-Ho Choi; Minh-Khai Nguyen; Young-Cheol Lim. 2019. "A Novel Space Vector Modulation Strategy for Three-Phase Quasi Switched Boost Inverter." 2019 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019 - ECCE Asia) , no. : 1.