Regis Leveugle

Prof. Regis Leveugle

Grenoble Alpes University, CNRS, Grenoble INP, TIMA, 38000 Grenoble, France
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Academic Career Length

23Years (2004-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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10 July 2006
Verified
Conference Paper
Closed access
PVP. Vanhauwaert
P. Vanhauwaert
RLRegis Leveugle
Regis Leveugle
PRP. Roche
P. Roche
12 December 2018 in IEEE Transactions on Device and Materials Reliability
Verified
Journal Article
Closed access
JDJean-Max Dutertre
Jean-Max Dutertre
VBVincent Beroulle
Vincent Beroulle
PCPhilippe Candelier
Philippe Candelier
SCStephan De Castro
Stephan De Castro
LFLouis-Barthelemy Faber
Louis-Barthelemy Faber
BRBruno Rouzeyre
Bruno Rouzeyre
Integrated circuits (ICs) laser illumination was originally used for emulation of radioactive ionizing particles effects on devices. Today, it is also a means for injecting faults into the computations of secure ICs for the purpose of retrieving secret data. The CMOS FD-SOI technology is expected to be less sensitive to laser fault injection than the more usual CMOS bulk technology. We report in this paper an experimental assessment of the interest of using FD-SOI rather than CMOS bulk to decrease laser sensitivity. Our experiments were conducted on test chips at the 28 nm node for both technologies with laser pulse durations in the picosecond and nanosecond ranges. We also discuss the interest of using bulk current sensors along with FD-SOI technology to achieve optimal detection of laser fault injection attempts.
1 October 2006
Verified
Conference Paper
Closed access
PVP. Vanhauwaert
P. Vanhauwaert
RLRegis Leveugle
Regis Leveugle
PRP. Roche
P. Roche
Fault-injection based dependability analysis has proved to be an efficient mean to predict the behavior of a circuit in presence of faults. Instrumentation-based techniques are in general used to perform the injection during simulation or emulation. The weak point of these techniques remains the characteristics obtained after modification of either the high-level description or the circuit netlist, especially when emulation is used. This paper proposes an instrumentation technique reducing the extra hardware and accelerating the fault injection campaigns thanks to optimized fault location addressing and parallel injection
1 January 2006
Verified
Conference Paper
Closed access
YMY. Monnet
Y. Monnet
MRM. Renaudin
M. Renaudin
RLRegis Leveugle
Regis Leveugle
NFN. Feyt
N. Feyt
PMP. Moitrel
P. Moitrel
FNF. M'Buwa Nzenguet
F. M'Buwa Nzenguet
This paper presents practical results on the evaluation of fault countermeasures implemented in an asynchronous DES coprocessor. The theory underlying the countermeasures was previously published in IOLTS 2005. For the first time this work reports a practical evaluation of fault countermeasures applied on asynchronous DES ASICs. Two DES crypto processors were fabricated using the 130 nm STmicroelectronics CMOS process; one as a reference and one hardened using a specific technique. This work enables us to compare the resistance of both circuits against fault injection and to validate the proposed countermeasures. The practical set-up of the fault injection, using a laser, is presented and the test campaign described. The practical results prove the efficiency of the method. The techniques can be applied to protect logic blocks in any applications
1 July 2007
Verified
Conference Paper
Closed access
YMY. Monnet
Y. Monnet
MRM. Renaudin
M. Renaudin
RLRegis Leveugle
Regis Leveugle
Asynchronous circuits are often claimed as being an interesting alternative to design robust systems against faults. In this study, a method is proposed to model the behavior of quasi delay insensitive (QDI) asynchronous circuits in the presence of SEUs (memory bit flips). The circuits and the fault injection process are both described using this model. The method, based on symbolic simulation, consists of exploring all the reachable states in the presence of faults in order to draw up an exhaustive list of behaviors. A case study shows that this method enables us to verify some properties on the circuits. SEU resistance can be formally proven using this analysis.
8 May 2018 in Information
Verified
Journal Article
Open access
PDF file
RLRegis Leveugle
Regis Leveugle
AMAsma Mkhinini
Asma Mkhinini
PMPaolo Maistri
Paolo Maistri
In the Internet of Things (IoT), many strong constraints have to be considered when designing the connected objects, including low cost and low power, thus limited resources. The confidentiality and integrity of sensitive data must however be ensured even when they have to be processed in the cloud. Security is therefore one of the design constraints but must be achieved without the usual level of resources. In this paper, we address two very different examples showing how embedded hardware/software co-design can help in improving security in the IoT context. The first example targets so-called “hardware attacks” and we show how some simple attacks can be made much more difficult at very low cost. This is demonstrated on a crypto-processor designed for Elliptic Curve Cryptography (ECC). A very lightweight countermeasure is implemented against Simple Power Analysis (SPA), taking advantage of the general processor usually available in the system. The second example shows how confidentiality in the cloud can be guaranteed by homomorphic encryption at a lower computational cost by taking advantage of a hardware accelerator. The proposed accelerator is very easy to implement and can easily be tuned to several encryption schemes and several trade-offs between hardware costs and computation speed.