Hierarchical classification, which organizes items into structured categories and subcategories, has emerged as a powerful solution for handling large and complex datasets. However, traditional flat classification approaches often overlook the hierarchical dependencies between classes, leading to suboptimal predictions and limited interpretability. This paper addresses these challenges by proposing a novel integration of tree-based models with hierarchical-aware split criteria through adjusted entropy calculations. The proposed method calculates entropy at multiple hierarchical levels, ensuring that the model respects the taxonomic structure during training. This approach aligns statistical optimization with class semantic relationships, enabling more accurate and coherent predictions. Experiments conducted on real-world datasets structured according to the GS1 Global Product Classification (GPC) system demonstrate the effectiveness of our method. The proposed model was applied using tree-based ensemble methods combined with the newly developed hierarchy-aware metric Penalized Information Gain (PIG). PIG was implemented with level-wise entropy adjustments, assigning greater weight to higher hierarchical levels to maintain the taxonomic structure. The model was trained and evaluated on two real-world datasets based on the GS1 Global Product Classification (GPC) system. The final dataset included approximately 30,000 product descriptions spanning four hierarchical levels. An 80-20 train–test split was used, with model hyperparameters optimized through 5-fold cross-validation and Bayesian search. The experimental results showed a 12.7% improvement in classification accuracy at the lowest hierarchy level compared to traditional flat classification methods, with significant gains in datasets featuring highly imbalanced class distributions and deep hierarchies. The proposed approach also increased the F1 score by 12.6%. Despite these promising results, challenges remain in scaling the model for very large datasets and handling classes with limited training samples. Future research will focus on integrating neural networks with hierarchy-aware metrics, enhancing data augmentation to address class imbalance, and developing real-time classification systems for practical use in industries such as retail, logistics, and healthcare.

Coordinating the movement of mobile robotic platforms (MRPs) in dynamic environments is a significant challenge in both civil and military applications, where large-scale transport, exploration, and task distribution are required. This research presents a neuro-fuzzy control system that integrates fuzzy logic with real-time navigation to optimize group movement. The system’s key components include data acquisition from navigation sensors such as gyroscopes, digital compasses, and lidars, along with wireless communication modules to facilitate seamless interaction and coordination among MRPs. A fuzzy logic controller, enhanced by neuro-like defuzzification, improves decision-making precision and platform synchronization. Additionally, the system incorporates advanced route planning algorithms to effectively manage group navigation, even in unpredictable and rapidly changing environments. The practical implementation is based on embedded platforms, including Raspberry Pi and microcontrollers such as STM8S003F3 and ESP32C3, which process data from sensors like the MPU-6050 gyroscope, QMC5883L compass, and YDLidar X4 lidar. This architecture was experimentally validated across real-world scenarios, demonstrating significant improvements in movement coordination, reduced response time, and enhanced operational efficiency. The system supports parallel processing and real-time optimization, making it suitable for tasks that require rapid adaptation to changing conditions. Furthermore, its scalability and flexibility make it an effective solution for real-world applications in environments that demand precise group control. The results underscore the practical value of this approach, reducing both development time and costs while improving the overall performance of MRP systems in complex operational settings. The developed neuro-fuzzy system provides a robust and scalable platform for efficient group management, making it well-suited for a wide range of dynamic, real-time applications.

Удосконалено метод сортування злиттям способом просторового розпаралелення процесу сортування, яке зведено до одночасного отримання елементів зростаючого та спадаючого масивів. Визначено та розглянуто такі основні етапи розроблення потокового графу для паралельного сортування масивів даних з використанням удосконаленого методу злиття, як декомпозиція алгоритму сортування масиву із m×N чисел, проектування комунікацій між функціональними операторами, укрупнення функціональних операторів, планування процесу сортування масиву із m×N чисел. Розроблено орієнтований на архітектуру графічного процесора конкретизований потоковий граф паралельного сортування масивів даних з використанням удосконаленого методу сортування злиттям. Запропоновано розробку програмних засобів паралельного сортування масивів даних з використанням удосконаленого методу злиття виконувати на основі комплексного підходу, який охоплює: дослідження, розроблення та вдосконалення алгоритмів і методів паралельного сортування масивів даних; потокові графи алгоритмів паралельного сортування; архітектуру графічного процесора GPU та програмну модель CUDA. Показано, що попри необхідність розроблення додаткових програм для внутрішніх операцій, а саме: створення тимчасових масивів для зберігання проміжних результатів, ядра програми, циклів виконання ядра програми у потоках та блоках, бінарного пошуку, присвоєння ключів записав на фінальній стадії порівняння двох масивів і формування вихідного відсортованого масиву, реалізація на графічному процесорі паралельного сортування масивів даних з використанням удосконаленого методу злиття, забезпечує значне зменшення часу сортування порівняно з використанням тільки центрального процесора.

The current stage of development of information technology is characterized by the expansion of the applications, much of which is associated with the accumulation of large data sets and parallel data searching in real-time. Such applications include automated systems for multi-level control of technological processes and complex objects, where at the lower levels of such systems is the accumulation of large data sets and their processing in real time. The main source in these systems are different sensors and devices that generate telemetric data. That is why it is very crucial to preprocess this data in real-time for finding further issues. One of the optimal ways for implementing it, is to use hardware approach like programmable logic device (PLD) with FPGA type. For resolving this issue in the article were analyzed the recent research and publications and has shown that the disadvantage of existing methods and algorithms for finding the maximum and minimum numbers in one-dimensional and two-dimensional arrays is that they are not focused on hardware implementation by using PLD with FPGA type. It is shown that the development of high-speed hardware for finding maximum and minimum numbers in one-dimensional and two-dimensional arrays should be carried out with an integrated approach, which includes methods, algorithms, structures and modern LPD and should be based on the following principles: homogeneity and regularity of structure; localization and simplification of connections between elements; modularity of construction; pipeline and spatial parallelism of data processing; consistency of the intensity of the discharge of bit sections with the intensity of their processing in the device. The basic operations for the implementation of algorithms for vertical-parallel search of maximum and minimum numbers in one-dimensional and two-dimensional arrays are highlighted and it is shown that they are based on the same type of basic operations with local and regular connections. In the article was developed the method of vertical-parallel searching of maximum and minimum numbers in arrays, which due to parallel processing of the first bit of an array of numbers and parallel formation of control words provides reduction of search time, which is mainly determined by bit numbers. Improved vertical-parallel method of simultaneous search of maximum and minimum numbers in two-dimensional arrays, which due to the simultaneous processing of p one-dimensional arrays and the use of the displacement method reduces the search time by p times compared to the existing method. It is shown that the time of vertical-parallel search of maximum and minimum numbers in one-dimensional and two-dimensional arrays is determined by the bit size of numbers, not their numbers. It is determined that the use of a common bus for formatting of the i-th bit of the maximum (minimum) number and the parallel formation of control words provides an increasing in the processing frequency of bit slices of one-dimensional array. It is determined that the amount of FPGA hardware resources that required for implementation a device for vertical-parallel searching of maximum and minimum numbers in a one-dimensional array mainly depends on the size of the array of numbers, and search time on their bit size.