Engineering can enhance students' theoretical knowledge and practical application skills when integrated into K‐12 education. This approach encourages students to contemplate technology and engineering in more depth. Field programmable gate array (FPGA) technology training is becoming increasingly important, especially for vocational high school technical teachers. This study focuses on providing FPGA technology training to these vocational and technical teachers. The aim is to improve their theoretical understanding of FPGA digital design and practical application skills. By incorporating the latest technology into their courses, educators can offer students in‐depth learning and practical experience in electronic engineering and digital design. The training program covered the basics of FPGA, its applications, and how it can benefit vocational high schools in laboratory environments. A total of 34 technical teachers participated in the training program. The effectiveness of the program was evaluated through pre‐ and posttraining questionnaires. The results showed that most of the questionnaire items were statistically and practically significant and varied according to the teachers' department, teaching experience, and level of education.

Bu çalışmada, PCB üretim sürecinde karşılaşılan olası kusurları otomatik olarak tespit ederek insan kaynaklı hataları en aza indirmeyi ve üretim sürecini hızlandırmayı amaçlayan; görüntü işleme tekniklerini ve derin öğrenme algoritmalarını kullanan bir kusur tespit ve sınıflandırma yöntemi önerilmiştir. Özellikle PCB üretim hattında böyle derin öğrenme tabanlı bir sistemin uygulanabilirliği değerlendirilmiş ve bu doğrultuda gerçek zamanlı bir simülasyon gerçekleştirilmiştir. Bu çalışmada farklı kusur türlerini içeren görüntülerden oluşan açık kaynaklı DeepPCB veri seti içinde yer alan 1194 PCB görüntüsü kullanılmıştır. Veri setinde yer alan görüntüler üzerinde toplam 7897 kusur etiketlenmiş ve bunlardan 6385 adedi (%80) eğitim, 1512 (%20) adedi ise test için ayrılmıştır. Eğitim ve test setleri, sınıflar arasında dengeli bir dağılım olacak şekilde rastgele bölünmüştür. Kusurlar, MakeSense yazılımı kullanılarak etiketlenmiş ve bu süreçte altı farklı kusur türü tanımlanmıştır. Etiketleme işlemi, modelin eğitim aşamasında yüksek doğruluk elde edilmesinde kritik bir adım olarak değerlendirilmiştir. YOLOv4 algoritmasıyla eğitilen model, mAP@50 değeri %64,1 olarak hesaplanmıştır. Daha güncel bir algoritma olan YOLOv8 kullanılarak eğitilen modelde ise mAP@50 değeri %93,5'e ulaşmıştır. Bu sonuçlar, YOLOv8 algoritmasının, PCB üretim hatlarında yüksek doğruluk oranı ve daha az hata ile uygulanabilir bir çözüm sunduğunu göstermektedir. Diğer taraftan bu modellerde, YOLOv4 ve v8’in varsayılan standart parametreleri kullanılmıştır. Ancak literatür taraması yapıldığında bu parametrelerin optimize edilmesinin daha yüksek performans elde edilmesinde önemli bir payı olduğu görülmüştür.

Field Programmable Gate Array (FPGA) is an integrated circuit (IC) that can be reprogrammed or configured by the customer or designer after production for rapid prototyping and post-process development. In this study, a cost-effective FPGA development board is designed to create basic engineering education applications and implement them in real-time. The FPGA development board utilizes an Altera Cyclone IV E-series chip and includes Bluetooth and Wi-Fi modules to provide a wider range of applications. This integration simplifies the use of wireless communication in various projects and applications for researchers and engineers. To verify the accuracy of the proposed board, simulations of selected digital designs and Bluetooth applications were first performed in VHDL (Very High Speed Integrated Circuit Hardware Description Language) using Intel® Quartus® Prime Lite Edition software. Then, experiments were performed on the board following the pin assignment configurations. It was observed that the developed applications worked successfully on the FPGA development board. As a result, this board, equipped with Bluetooth and Wi-Fi modules, offers a fast and cost-effective solution for users in various fields such as mobile, robotics, smart home systems, and remote monitoring and control devices

The increasing global population, combined with the impacts of climate change and global warming, has made the production of high-quality agricultural products at lower costs a critical necessity. Addressing these challenges requires leveraging emerging technologies. This study presents a prototype system that integrates digital twin technology into greenhouse farming. A physical greenhouse was equipped with a Raspberry Pi and various environmental sensors to collect real-time data. This data is visualized and managed through a Unity 3D-based digital twin, enabling automated control via rule-based decision logic. Monitored parameters include temperature, humidity, light intensity, and soil moisture, which dynamically trigger irrigation, ventilation, and lighting mechanisms. The system was tested over a seven-day period under different lighting scenarios. Results showed consistent system performance, demonstrating its viability for educational use and small-scale agricultural applications. Furthermore, the flexible architecture of the system suggests potential for future extension toward predictive modeling and adaptive control strategies.

The Secure Hash Algorithm (SHA)-256 is a widely used cryptographic hash function in modern information security systems. This study presents the design and comparative analysis of a SHA-256 hardware accelerator implemented on a Field Programmable Gate Array (FPGA) using two hardware development methodologies: a Register Transfer Level (RTL)-based Hardware Description Language (HDL, Verilog) approach and a High-Level Synthesis (HLS) approach. In the HLS-based methodology, the SHA-256 core was developed in the C programming language and synthesized into an Advanced eXtensible Interface (AXI)-compliant Intellectual Property (IP) core using an HLS tool, followed by system integration in the Vivado design environment. In contrast, the RTL-based approach involved designing an equivalent SHA-256 IP core fully described at the RTL level using Verilog and integrating it into the same system architecture. Verification of the HLS-based design was performed using C-level simulations and C/RTL co-simulations, while the RTL-based design was functionally verified using a dedicated testbench in the Vivado environment. Both hardware accelerators were integrated with a processor system using the Vivado Block Design tool and implemented on the Python Productivity for Zynq (PYNQ)-Z1 FPGA platform operating at a target clock frequency of 100 MHz. Post-implementation results indicate that the HLS-based design consumed more hardware resources, whereas the RTL-based design achieved a more resource-efficient implementation. Both designs met timing constraints and provided approximately a 16× performance improvement compared to a software-based SHA-256 implementation. Overall, the results highlight the trade-off between development efficiency and hardware optimization offered by HLS and RTL approaches, respectively.

Evolving counterfeiting techniques have turned counterfeit banknote detection into a multidimensional problem that can no longer be fully addressed through traditional security measures alone. While artificial intelligence (AI), particularly convolutional neural networks (CNNs), has emerged as a promising solution, its success remains heavily dependent on training data quality. Access to genuine images is restricted by copyright and central bank regulations, forcing a reliance on synthetic data, which often triggers domain shift and reliability issues. This study employs a comparative case analysis, treating the Turkish and international ecosystems as two primary macro-cases evaluated against legal, ethical, technical, and accessibility criteria. By establishing a causal linkage between technical errors and their resulting legal liabilities, the research explicitly differentiates between the criminal and civil consequences of misclassification. The findings indicate that focusing solely on technical accuracy is insufficient. Systemic limitations related to dataset transparency, regulatory compliance, and accessibility implementation represent common weaknesses in both settings. Consequently, the study proposes a lifecycle-anchored governance assessment rubric that aligns technical performance with legal accountability and inclusive design principles, providing a replicable evaluative instrument for the trustworthy deployment of AI in financial security applications.