2022: Post Doctoral in Physical Department at University of São Paulo, São Paulo/SP Brazil. Development of the SAMPA chip and SRS integration project. Xilinx FPGA Virtex 6 programming code (in VHDL and Verilog languages) in FEC card system from RD51 group at CERN, as FAPESP (São Paulo state research foundation) fellow. 2007-2012 Digital designer of Integrated Circuits at at University of São Paulo, São Paulo/SP Brazil. - As CNPQ (Brazilian main federal research center) fellow as digital designer, using VHDL and Verilog languages in Cadence Systems to create Integrated Circuits. Also, ModelSim tool to debug the logic of developed digital circuits. Used Altera Cyclone V FPGA and Microcontrollers to create I.C. test environment. 2010: PhD in Electrical Engineering at University of São Paulo, São Paulo/SP Brazil. - PhD thesis on the development of the digital part of a Multicore PIC Microcontroller, using a Xilinx Virtex II FPGA for a proof of concept, programming an FPGA with four PIC microcontroller cores. 2004: MSc degree in Computer Science. Development of a VDHL version of PIC16F Microcontroller, fully compatible with microchip PIC16F instruction set and timing. Use of FPGA Xilinx SPARTAN for a proof of concept. 2002: BSc degree in Computer Science. - An additional study of several Microcontrollers, VHDL and Verilog languages. Languages: VHDL, Verilog, C, Assembly Both IDEs and FPGA Altera (Intel) or Xilinx (AMD) Deep use and knowledge of ModelSim tool RISC-V architecture