The apparent saturation of aggressive Moore's law scaling of semiconductor technologies is pushing the boundaries of traditional packaging and integration schemes to accommodate the ever-growing data bandwidth and heterogeneity demands. In this article, we demonstrate the silicon-interconnect fabric (Si-IF) technology as a superior alternative to conventional printed circuit boards (PCBs) to enhance system scaling. The Si-IF is a silicon-based, package-less, fine-pitch, highly scalable, heterogeneous integration platform to assemble and integrate massive wafer-scale systems. In this technology, dielets are closely assembled on the Si-IF at small interdielet spacings ( ≤ 50 μm) using fine-pitch ( ≤ 10 μm) die-to-substrate interconnects allowing for tight integration on a system-level package. To achieve these fine-pitch interconnects, a novel assembly technique using solder-less direct metal-metal [copper-copper (Cu-Cu)] thermal compression bonding was developed. Using this process, sub-10- μm-pitch interconnects with a low specific contact resistance of ≤ 0.7 Ω·μm ² and high shear force of 90 N for 4-mm ² dies were successfully demonstrated. Moreover, these fine-pitch interconnects combined with the small interdie spacing provide a large number of parallel short links ( ≤ 500 μm) with low loss (≤2 dB) for interdielet communication that is comparable to on-chip connections. Consequently, simple buffers can transfer data between dies using a Simple Universal Parallel intERface for chips (SuperCHIPS) protocol at low link latency (<; 20 ps), low energy per bit (≤0.03 pJ/b), and high data rates (up to 10 Gb/s/link), corresponding to an aggregate data bandwidth of up to 8 Tb/s/mm. The benefits of the SuperCHIPS interface are experimentally demonstrated using functional dielet assembly on the Si-IF to show 4- 23× higher data bandwidth, 3- 65× lower latency, and 5- 40× lower energy per bit compared to existing integration schemes.

This paper reviews advances in die/dielet-to-dielet (D2D), dielet-to-wafer (D2W) and dielet-to-substrate integration for advanced packaging. Key D2D and D2W integration approaches such as solder flip-chip, solderless thermal compression bonding, and copper/dielectric hybrid bonding, are identified and analyzed. For each method, the underlaying mechanism, influencing factors, challenges, and state of the art implementations are discussed. Additionally, these methods are compared based on mechanical and electrical reliability studies from the literature to delineate the design space for their application in advanced packaging.

Thin film Si1-xGex alloys have been grown on silicon by molecular beam epitaxy with nominal composition, x, between 10 and 20 at %. These heterostructures have several applications in band-engineering and in the field of device structures. Film thicknesses, germanium atomic fractions and tetragonal distortion were determined by three different techniques, i.e. Rutherford Backscattering Spectrometry-Channeling, Analytical Electron Microscopy and Double Crystal X-ray Diffractometry. The good agreement found between the various analytical results demonstrates that each technique is capable of a high level of accuracy and consistency. These characterization methods are therefore powerful tools for the precise control of the epitaxial layer growth parameters for the fabbrication of different device structures

In this letter, we propose a novel signaling figure of merit (s-FoM) for comparison of signaling schemes across different packaging technologies. It considers all the essential metrics that affect system performance and efficiency and combines them in a simple, easily quantifiable manner. These include energy per bit, data-bandwidth per unit shoreline, latency, length of the link, and real-estate overhead. This tool captures all the performance trade-offs and enables a fair comparison across different packaging platforms and integration schemes.