Dr. Sezer Goren

Electrical and Computer Engineering, University of Massachusetts Dartmouth, New Bedford, Massachusetts, USA

Dr. Sezer Goren

Electrical and Computer Engineering, University of Massachusetts Dartmouth, New Bedford, Massachusetts, USA

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Academic Career Length

24Years (2003-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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31 January 2007 in Computers and Electrical Engineering

Journal Article

On state reduction of incompletely specified finite state machines

Sezer Goren

F. Joel Ferguson

23 May 2017 in IEEE Transactions on Computers

Journal Article

Hardware Division by Small Integer Constants

H. Fatih Ugurdag

Florent de Dinechin

Y. Serhan Gener

Sezer Goren

Laurent-Stephane Didier

This article studies the design of custom circuits for division by a small positive constant. Such circuits can be useful for specific FPGA and ASIC applications. The first problem studied is the Euclidean division of an unsigned integer by a constant, computing a quotient and remainder. Several new solutions are proposed and compared against the state-of-the-art. As the proposed solutions use small look-up tables, they match well with the hardware resources of an FPGA. The article then studies whether the division by the product of two constants is better implemented as two successive dividers or as one atomic divider. It also considers the case when only a quotient or only a remainder is needed. Finally, it addresses the correct rounding of the division of a floating-point number by a small integer constant. All these solutions, and the previous state-of-the-art, are compared in terms of timing, area, and area-timing product. In general, the relevance domains of the various techniques are different on FPGA and on ASIC.

3 April 2014 in IEEE Transactions on Computers

Journal Article

Fast and Efficient Circuit Topologies forFinding the Maximum of n k-Bit Numbers

Bilgiday Yuce

H. Fatih Ugurdag

Sezer Goren

Gunhan Dundar

Finding the value and/or index of the maximum (or minimum) element of a set of n numbers (each with k-bits) is a fundamental arithmetic operation and is needed in many applications. This paper proposes several maximum-finder (or minimum-finder) circuit topologies, which are parallel. We wrote circuit generators at hardware description language level for our topologies and previous works. Then we synthesized these circuits for 20 different (n, k) cases (with values up to 64) and compared their efficiency in timing (latency), area, and energy. The timing complexity of our fastest topology is O(log n + log k), whereas the fastest in the literature is O(log n log k). The synthesis results showed that our fastest topology is 1.2-2.2 times (1.6 times on the average) faster than the state-of-the-art. In this paper, we argue that a more fair metric of area efficiency is area-timing product. In terms of ATP, our proposed topologies are better than the state-of-the-art in 19 out of the 20 cases. In terms of energy (i.e., power-timing product, abbreviated as PTP), we are better in 11 cases out of 20.

12 October 2014

Conference Paper

Fault attack on AES via hardware Trojan insertion by dynamic partial reconfiguration of FPGA over ethernet

Anju Johnson

Sayandeep Saha

Rajat Subhra Chakraborty

Debdeep Mukhopadhyay

Sezer Goren

1 February 2013 in Computers and Electrical Engineering

Journal Article

Partial bitstream protection for low-cost FPGAs with physical unclonable function, obfuscation, and dynamic partial self reconfiguration

Sezer Goren

Ozgur Ozkurt

Abdullah Yildiz

H. Fatih Ugurdag

Rajat S. Chakraborty

Debdeep Mukhopadhyay

1 March 2017 in Integration

Journal Article

Fast Multiplier Generator for FPGAs with LUT based Partial Product Generation and Column/row Compression

Ahmet Kakacak

Aydin Emre Guzel

Ozan Cihangir

Sezer Goren

H. Fatih Ugurdag

About Me

Dr. Sezer Goren received her BS and MS degrees in Electrical and Electronics Engineering from Bosphorus University, Istanbul, Turkiye, and a PhD degree in Computer Engineering from University of California, Santa Cruz, USA. She had full-time industry work in Silicon Valley between 1998 and 2005, mostly as a senior verification engineer, and employers include SynTest, Cadence, Apple, Switch-On Networks (PMC-Sierra), and Aarohi Communications (Emulex). Later, she made a transition into academia and worked as an assistant professor at Bahcesehir University between 2005 and 2010 and then as a full professor in the Computer Engineering Department of Yeditepe University, Istanbul, Turkiye, between 2010 and 2023. She served as the department chair between 2016 and 2020 and the IEEE Computer Society Turkiye Chapter chair between 2021 and 2023. She worked as the primary investigator of 3 funded projects, supervised 18 MS and 4 PhD theses to completion, and published a total of 85 journal and conference publications. Her research interests include design automation of digital systems, design verification and test, reconfigurable computing, embedded system design, hardware security, computer arithmetic, deep learning, and edge AI.

Dr. Sezer Goren

Dr. Sezer Goren

Research Focus & Metrics

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Representative Publications

About Me