The progression of SiC MOSFET technology from planar to trench structures requires optimized gate oxide layers within the trench to enhance device performance. In this study, we investigated the interface characteristics of HfO₂ and SiO₂/HfO₂ gate dielectrics grown by atomic layer deposition (ALD) on SiC trench structures. The trench structure morphology was revealed using scanning electron microscopy (SEM). Atomic force microscopy (AFM) measurements showed that the roughness of both films was below 1nm. Spectroscopic ellipsometry (SE) indicated that the physical thicknesses of HfO₂ and SiO₂/HfO₂ were 38.275 nm and 40.51 nm, respectively, demonstrating their comparable thicknesses. X-ray photoelectron spectroscopy (XPS) analysis of the gate dielectrics revealed almost identical Hf 4f core levels for both HfO₂ and the SiO₂/HfO₂ composite dielectrics, suggesting that the SiO₂ interlayer and the SiC substrate had minimal impact on the electronic structure of the HfO₂ film. The breakdown electric field of the HfO₂ film was recorded as 4.1 MV/cm, with a leakage current at breakdown of 1.1 × 10⁻³A/cm². The SiO₂/HfO₂ stacked film exhibited significantly better performance, with a breakdown electric field of 6.5 MV/cm and a marked reduction in leakage current to 3.7 × 10⁻⁴ A/cm². A detailed extraction and analysis of the leakage current mechanisms were proposed, and the data suggested that the introduction of thin SiO₂ interfacial layers effectively mitigated small bandgap offset issues, significantly reducing leakage current and improving device performance.

The transition of SiC MOSFET structure from planar to trench-based architectures requires the optimization of gate dielectric layers to improve device performance. This study utilizes a range of characterization techniques to explore the interfacial properties of ZrO₂ and SiO₂/ZrO₂ gate dielectric films, grown via atomic layer deposition (ALD) in SiC epitaxial trench structures to assess their performance and suitability for device applications. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) measurements showed the deposition of smooth film morphologies with roughness below 1 nm for both ZrO₂ and SiO₂/ZrO₂ gate dielectrics, while SE measurements revealed comparable physical thicknesses of 40.73 nm for ZrO₂ and 41.55 nm for SiO₂/ZrO₂. X-ray photoelectron spectroscopy (XPS) shows that in SiO₂/ZrO₂ thin films, the binding energies of Zr 3d_5/2 and Zr 3d_3/2 peaks shift upward compared to pure ZrO₂. Electrical characterization showed an enhancement of E_BR (3.76 to 5.78 MV·cm⁻¹) and a decrease of I_{ON_EBR} (1.94 to 2.09 × 10⁻³ A·cm⁻²) for the SiO₂/ZrO₂ stacks. Conduction mechanism analysis identified suppressed Schottky emission in the stacked film. This indicates that the incorporation of a thin SiO₂ layer effectively mitigates the small bandgap offset, enhances the breakdown electric field, reduces leakage current, and improves device performance.

This study proposed an innovative method for growing gate oxide on silicon carbide (SiC), where silicon oxide (SiO₂) was fabricated on a deposited Al₂O₃ layer, achieving high quality gate oxide. A thin Al₂O₃ passivation layer was deposited via atomic layer deposition (ALD), followed by Si deposition and reoxidation to fabricate a MOS structure. The effects of different ALD growth cycles on the interface chemical composition, trap density, breakdown characteristics, and bias stress stability of the MOS capacitors were systematically investigated. X-ray photoelectron spectroscopy (XPS) analyses revealed that an ALD Al₂O₃ passivation layer with 10 growth cycles effectively suppresses the formation of the proportion of Si-O_xC_y bonds. Additionally, the SiO₂/Al₂O₃/SiC gate stack with 10 ALD growth cycles exhibited optimal electrical properties, including a minimum interface state density (D_it) value of 3 × 10¹¹ cm⁻² eV⁻¹ and a breakdown field (E_bd) of 10.9 MV/cm. We also systematically analyzed the bias stress stability of the capacitors at room temperature and elevated temperatures. Analysis of flat-band voltage (ΔV_fb) and midgap voltage (ΔV_mg) hysteresis after high-temperature positive and negative bias stress demonstrated that incorporating a thin Al₂O₃ layer at the interface is the key factor in enhancing the stability of V_fb and midgap voltage V_mg.