This paper presents a Dual-Core LockStep (DCLS) implementation to protect hard-core processors against radiationinduced soft errors. The proposed DCLS is applied to an ARM Cortex-A9 embedded processor. Different software optimizations were evaluated to assess their impact on performance and fault tolerance. Heavy ions experiments and fault injection emulation were performed to analyze the system susceptibility to errors and the DCLS performance. Results show that the approach is able to decrease the system cross-section and achieve high protection against errors. The DCLS successfully protects the system from up to 78% of the injected faults. The execution performance analysis shows that by reducing the number of verifications and augmenting the block partition execution time it is possible to increase the system reliability with minimal performance losses.

This work evaluates the RISC-V Rocket processor embedded in a COTS SRAM-based FPGA under heavy-ion induced faults and emulation fault injection. We also analyze the efficiency of using mitigation techniques based on hardware redundancy and scrubbing. Results demonstrated an improvement of 3× in the cross-section when scrubbing and coarse grain triple modular redundancy are used. The Rocket processor presented analogous sensitivity to radiation effects as the state-of-the-art soft-processors. Due to the complexity of the system-on-chip, not only the Rocket core but also its peripherals should be protected with proper solutions. Such solutions should address the specific vulnerabilities of each component to improve the overall system reliability while maintaining the trade-off with performance.

This work proposes a novel methodology to evaluate SRAM-based FPGA's susceptibility with respect to Single-Event Upset (SEU) as a function of noise on VDD power pins, TotalIonizing Dose (TID) and TID-imprinted effect on BlockRAM cells. The proposed procedure is demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8 MV Pelletron accelerator for the SEU test with heavy-ions, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. In order to observe the TID-induced imprint effect inside the BlockRAM cells, a second SEU test with neutrons was performed with Americium/Beryllium ( ²⁴¹ AmBe). The noise was injected into the power supply bus according to the IEC 61.000-4-29 standard and consisted of voltage dips with 16.67% and 25% of the FPGA's VDD at frequencies of 10 Hz and 5 kHz, respectively. At the end of the experiment, the combined SEU failure rate, given in error/bit.day, is calculated for the FPGA's BlockRAM cells. The combined failure rate is defined as the average SEU failure rate computed before and after exposition of the FPGA to the TID.

The recent advance of silicon technology has allowed the integration of complex systems in a single chip. Nowadays, Field Programmable Gate Array (FPGA) devices are composed not only of the programmable fabric but also by hard-core processors, dedicated processing block interfaces to various peripherals, on-chip bus structures and analog blocks. Among the latest released devices of this type, this work focuses in the 28 nm Xilinx Zynq-7000 All Programmable SoC (APSoC). While not immune to the radiation environment in space, the Zynq-7000 seems to be very attractive for the aerospace sector due to its high computational power capability and low-power consumption. In this work, results from heavy ions testing for Zynq-7000 are presented. The experiments were performed in a Brazilian facility located at the University of São Paulo, Brazil.