The field‐effect conductance activation energy E_a as a function of the gate voltage V_g is investigated for polycrystalline silicon thin‐film transistors. An analytical expression for E_a is obtained for various models of the bulk and interface states. Using a computer minimization program to fit the experimental E_a vs V_g data with the theory, the energy distribution of the bulk states and the interface states are separated for nonhydrogenated and hydrogenated polycrystalline silicon thin‐film transistors. In both cases, the bulk states have exponential band tails and a wide peak near the midgap and the interface states have an exponential distribution from the band edge.

An analytical compact drain current model for undoped (or lightly doped) short-channel triple-gate fin-shaped field-effect transistors (finFETs) is presented, taking into account quantum-mechanical and short-channel effects such as threshold-voltage shifts, drain-induced barrier lowering, and subthreshold slope degradation. In the saturation region, the effects of series resistance, surface roughness scattering, channel length modulation, and saturation velocity were also considered. The proposed model has been validated by comparing the transfer and output characteristics with device simulations and with experimental results. The good accuracy and the symmetry of the model make it suitable for implementation in circuit simulation tools.

A model for the grain-boundary barrier height of undoped polycrystalline silicon thin-film transistors is developed based on a rodlike structure of the grains with a square cross section and a Gaussian energy distribution of the trapping states at the grain boundaries. An analytical expression for the threshold voltage is derived in terms of the distribution parameters of the grain-boundary trapping states, the grain size, and the gate oxide thickness. Comparison between the developed model and the experimental drain current versus gate voltage data has been made and excellent agreement was obtained. The key parameters affecting the threshold voltage and the channel conductance of the transistor were investigated by computer stimulation. The threshold voltage is mainly affected by the grain size and the gate oxide thickness. For the improvement of the channel conductance, besides the passivation of the grain-boundary trapping states, the increase of the grain size and mainly the scaling down of the gate oxide thickness are the key factors.

The low frequency noise technique is used to obtain the volume profile of traps in the ${\text{SiN}}_{\text{x}}$ gate dielectric of hydrogenated amorphous silicon (a-Si:H) and nanocrystalline silicon (nc-Si:H) thin film transistors (TFTs). In both a-Si:H and nc-Si:H TFTs, within the range of probing depth in the gate dielectric, the traps have a uniform spatial distribution which is consistent with the observed pure 1/f noise. The experimental results show that the gate dielectric trap properties near the interface are dependent on the channel material with the trap density in nc-Si:H TFTs being much smaller in comparison with the a-Si:H TFTs.