Vertical meta-grating couplers (VMGCs), while essential for flexible spatial beam coupling in meta-photonic integrated circuits (MPICs), suffer from inherently low coupling efficiency that hinders broader applications. In this study, we introduce an improved adjoint optimization method with high computational efficiency and excellent optimization effectiveness. Utilizing this method, we demonstrate an ultra-compact single-polarization VMGC achieving 81.57% coupling efficiency with a 92 nm 3 dB bandwidth, and a dual-polarization beam-splitting coupler with over 52% coupling efficiency for both polarizations, a 3 dB bandwidth exceeding 60 nm, an ultra-high extinction ratio of over 26.4 dB, and negligible polarization dependent loss at 1550 nm. To the best of our knowledge, this achievement represents the best simulation record to date for a perfect vertical coupler without bottom reflectors.

Efficient and compact grating coupler designs are crucial for enhancing the performance of photonic integrated chips. In this work, we propose a design approach that combines metalens technology and topology optimization. As a proof of concept, we first designed an on-chip metalens to preliminarily improve the transmission efficiency of a compact mode converter. Building upon this, we applied a topology optimization algorithm to further optimize the tapered conversion region, compensating for the insertion loss caused by local periodic approximations in the metalens design. This process ultimately improved the transmission efficiency to 93.69%. By integrating this with the previously designed grating coupler, we experimentally demonstrated that the mode converter, with a size of 20 × 12 μm and a minimum feature size greater than 180 nm, achieves an insertion loss of only −0.4 dB. The compact grating coupler, designed within a 35 × 12 μm footprint, shows an insertion loss of −3.6 dB at a wavelength of 1550 nm.

Analog optical computing has garnered significant attention owing to its ultra-high speed, ultra-low power consumption, and parallel processing capabilities. Recent advances in Fourier optics and metasurface technology have enabled the realization of on-chip optical differentiators, integrators, and differential equation solvers. However, conventional devices are constrained to a single function once fabricated, lacking dynamic reconfigurability. In this study, we propose an on-chip reconfigurable analog optical computing device based on a silicon-on-insulator platform. The design employs a modified 4f system, where the air-slit structure in the computational metasurface is replaced with phase-change material (Ge ₂ Sb ₂ Te ₅ and Sb ₂ S ₃ ) array blocks. By independently controlling the phase transition of each block, we demonstrate dynamic switching between differentiation, integration, ordinary differential equation solving, and integro-differential equation (IDE) solving within a fixed structure. The IDE solving is first implemented on-chip. Theoretically, this device can be reconfigured for arbitrary computational operations. Our approach offers a promising solution for the large-scale integration of optical computing chips, with potential applications in high-speed, complex computations for artificial intelligence.