Suspended membranes of monatomic graphene exhibit great potential for applications in electronic and nanoelectromechanical devices. In this work, a "hot and dry" transfer process is demonstrated to address the fabrication and patterning challenges of large-area graphene membranes on top of closed, sealed cavities. Here, "hot" refers to the use of high temperature during transfer, promoting the adhesion. Additionally, "dry" refers to the absence of liquids when graphene and target substrate are brought into contact. The method leads to higher yields of intact suspended monolayer chemical vapor deposition (CVD) graphene and artificially stacked double-layer CVD graphene membranes than previously reported. The yield evaluation is performed using neural-network-based object detection in scanning electron microscopy (SEM) images, ascertaining high yields of intact membranes with large statistical accuracy. The suspended membranes are examined by Raman tomography and atomic force microscopy (AFM). The method is verified by applying the suspended graphene devices as piezoresistive pressure sensors. Our technology advances the application of suspended graphene membranes and can be extended to other two-dimensional materials.

In this paper, we present our work developing a family of silicon-on-insulator (SOI)–based high-g micro-electro-mechanical systems (MEMS) piezoresistive sensors for measurement of accelerations up to 60,000 g. This paper presents the design, simulation, and manufacturing stages. The high-acceleration sensor is realized with one double-clamped beam carrying one transversal and one longitudinal piezoresistor on each end of the beam. The four piezoresistors are connected to a Wheatstone bridge. The piezoresistors are defined to 4400 Ω, which results in a width-to-depth geometry of the pn-junction of 14 μm × 1.8 μm. A finite element method (FEM) simulation model is used to determine the beam length, which complies with the resonance frequency and sensitivity. The geometry of the realized high-g sensor element is 3 × 2 × 1 mm³. To demonstrate the performance of the sensor, a shock wave bar is used to test the sensor, and a Polytec vibrometer is used as an acceleration reference. The sensor wave form tracks the laser signal very well up to 60,000 g. The sensor can be utilized in aerospace applications or in the control and detection of impact levels.

A novel capacitive sensor for measuring the water-level and monitoring the water quality has been developed in this work by using an enhanced screen printing technology. A commonly used environment-friendly conductive polymer poly(3,4-ethylenedioxythiophene):poly (styrenesulfonate) (PEDOT:PSS) for conductive sensors has a limited conductivity due to its high sheet resistance. A physical treatment performed during the printing process has reduced the sheet resistance of printed PEDOT:PSS on polyethylenterephthalat (PET) substrate from 264.39 Ω/sq to 23.44 Ω/sq. The adhesion bonding force between printed PEDOT:PSS and the substrate PET is increased by using chemical treatment and tested using a newly designed adhesive peeling force test. Using the economical conductive ink PEDOT:PSS with this new physical treatment, our capacitive sensors are cost-efficient and have a sensitivity of up to 1.25 pF/mm.

In this paper we present a printed, fast, high-sensitive and cheap wireless incontinence sensor

This paper presents prime results on process development and optimization of dry etching of silicon carbide (SiC) for via formation and deep etching for SiC-based microsystems. The investigations and corresponding results of the process developments enable the first realization of a full SiC-based technological demonstrator composed of a SiC-interposer with a flip chip mounted deep etched MEMS SiC Device. By optimizing the process, etch depth of 200μm with an etch rate of up to 2μm/min can be achieved for via etching. In addition, a Design Of Experiments (DOE) with a total of 29 experiments with seven factors was done to characterize the deep etching of large areas into the silicon carbide. Hereby, vertical sidewalls with low micro masking, low micro trenching and an etch rate of up to 4 μm / min could be achieved. The findings and optimized processes were implemented to develop on the one hand a 200 μm thick SiC interposer with copper metallization. On the other hand, a SiC-MEMS Device was manufactured with a deep etched cavity in SiC bulk wafer forming by the end a 50 μm thin membrane. The results demonstrate the ability of etching monocrystalline SiC with a high etch rate, enabling new fundamental topologies/structures and packaging concepts for harsh environments micro electromechanical systems (MEMS) and high-power electronics. The developed etching technologies demonstrate and enable various applications for 3D Integration with wide bandgap substrates taking advantage of the superior electrical and mechanical properties of SiC.

In the present work we investigate the quality of low temperature Plasma Enhanced Chemical Vapor Deposition (PECVD) and plasma treated Tetraethyl orthosilicate (TEOS)-based TSV-liner films. Different designs of Trough Silicon Via (TSV) Test structures with 10μm and 20μm width and a depth of 100μm have been fabricated. Two differently doped silicon substrates have been used – highly p-doped and moderately doped. The results for break-through, resistivity and capacitance for the 20μm structures show a better performance compared to the 10μm structures. This is mainly due to increased liner thickness in the reduced aspect ratio case. Lower interface traps and oxide charge densities have been observed in the C-V measurements results for the 10μm structures.