Intra coding plays a crucial role in the High Efficiency Video Coding (HEVC) standard. It provides the higher coding efficiency than the previous standard, H.264/Advanced Video Coding. The block partitioning in HEVC supports quad-tree-based coding unit (CU) structure from size 64×64 to 8×8. The new technique provides better performances on one hand, whereas on the other hand it also increases the coding complexity. In this paper, a novel fast algorithm is proposed for the CU size decision in intra coding. Both the global and local edge complexities in horizontal, vertical, 45° diagonal, and 135° diagonal directions are proposed and used to decide the partitioning of a CU. Coupled with handling its four sub-CUs in the same way, a CU is decided to be split, nonsplit, or undetermined for each depth. Compared with the reference software HM10.0, the encoding time is reduced by ~52% on average, with ~0.8% Bjontegaard Distortion-rate increasing and reasonable peak signal-to-noise ratio losses.

Polynomial multiplication is the basic and most computationally intensive operation in ring-learning with errors (ring-LWE) encryption and "somewhat" homomorphic encryption (SHE) cryptosystems. In this paper, the fast Fourier transform (FFT) with a linearithmic complexity of O(nlogn), is exploited in the design of a high-speed polynomial multiplier. A constant geometry FFT datapath is used in the computation to simplify the control of the architecture. The contribution of this work is three-fold. First, parameter sets which support both an efficient modular reduction design and the security requirements for ring-LWE encryption and SHE are provided. Second, a versatile pipelined architecture accompanied with an improved dataflow are proposed to obtain a high-speed polynomial multiplier. Third, the proposed architecture supports polynomial multiplications for different lengths n and moduli p. The experimental results on a Spartan-6 FPGA show that the proposed design results in a speedup of 3.5 times on average when compared with the state of the art. It performs a polynomial multiplication in the ring-LWE scheme (n=256,p=1049089) and the SHE scheme (n=1024,p=536903681) in only 6.3 μs and 33.1 μs, respectively.

This paper presents a ΣΔ modulator based on a gain-boost class-C inverter for audio applications. The gain-boost class-C inverter behaves as a low-voltage subthreshold amplifier and boosts its dc gain for the high-precision requirement. Meanwhile, an on-chip body bias is used to compensate the performance degradation of the inverter at a slow process corner or low supply voltage. The proposed inverter-based modulator is fabricated in a 65-nm mixed-signal CMOS process with a die area of 0.3 mm ² . The experimental chip achieves 91-dB peak signal-to-noise-plus-distortion ratio (SNDR), 94-dB signal-to-noise ratio (SNR) and 98-dB dynamic range (DR) over a 20-KHz audio band with a 5-MHz sampling frequency and a 0.8-V supply voltage consuming only 230-μW power, which demonstrates that the gain-boost class-C inverter is particularly suitable for low-voltage micro-power high-resolution applications.

Polynomial multiplication is the key and time-consuming operation among various operators in Post-Quantum Cryptography (PQC), which aims to find quantum-resistant algorithms to prevent attacks launched by quantum computers. Number Theoretic Transform (NTT) is an efficient algorithm that can accelerate the polynomial multiplication from $\mathcal {O}(n^{2})$ to $\mathcal {O}(nlog(n))$ . In this brief, we present a pipelined NTT (PipeNTT) hardware architecture in FPGA to achieve high throughput with fewer hardware resources. The dataflow and the butterfly unit are optimized to minimize the latency. To fulfil the proposed dataflow, a Block RAM (BRAM) based reordering unit is designed to further reduce the hardware resource. Moreover, our architecture can also be applied to Inverse-NTT (INTT). Compared to state-of-the-art parallel designs, our design achieves a 30% lower area-time product with 3x less memory space requirement.

Ternary content addressable memories (TCAMs) perform high-speed lookup operation but when compared with static random access memories (SRAMs), TCAMs have certain limitations such as low storage density, relatively slow access time, low scalability, complex circuitry, and are very expensive. Thus, can we use the benefits of SRAM by configuring it (with additional logic) to enable it to behave like TCAM? This brief proposes a novel memory architecture, named Z-TCAM, which emulates the TCAM functionality with SRAM. Z-TCAM logically partitions the classical TCAM table along columns and rows into hybrid TCAM subtables, which are then processed to map on their corresponding memory blocks. Two example designs for Z-TCAM of sizes 512 × 36 and 64 × 32 have been implemented on Xilinx Virtex-7 field-programmable gate array. The design of 64 × 32 Z-TCAM has also been implemented using OSUcells library for 0.18 μm technology, which confirms the physical and technical feasibility of Z-TCAM. Search latency for each design is three clock cycles. The detailed implementation results and power measurements for each design have been reported thoroughly.

We present an automated methodology for producing hardware-based random number generator (RNG) designs for arbitrary distributions using the inverse cumulative distribution function (ICDF). The ICDF is evaluated via piecewise polynomial approximation with a hierarchical segmentation scheme that involves uniform segments and segments with size varying by powers of two which can adapt to local function nonlinearities. Analytical error analysis is used to guarantee accuracy to one unit in the last place (ulp). Compact and efficient RNGs that can reach arbitrary multiples of the standard deviation sigma can be generated. For instance, a Gaussian RNG based on our approach for a Xilinx Virtex-4 XC4VLX100-12 field-programmable gate array produces 16-bit random samples up to 8.2 sigma. It occupies 487 slices, 2 block-RAMs, and 2 DSP-blocks. The design is capable of running at 371 MHz and generates one sample every clock cycle.