As chip interconnect density increases, routing problems become increasingly complex. The routing scheme significantly impacts key performance indicators such as chip delay, power consumption, and area. In Very Large-Scale Integration (VLSI) routing, the rectilinear Steiner minimal tree is an excellent interconnect model for multi-pin nets. However, modern VLSI designs require multi-layer obstacle-avoiding routing, where wires must traverse multiple metal layers while avoiding obstacles to ensure connectivity and performance. This makes the Multi-Layer Obstacle-Avoiding Rectilinear Steiner Minimal Tree (ML-OARSMT) problem highly challenging in VLSI physical design. To address this issue, this paper proposes an ML-OARSMT construction algorithm based on deep reinforcement learning. First, a multi-layer obstacle-avoiding spanning graph is constructed by introducing vertex mapping, which connects different layers to handle the multi-layer obstacle-avoiding routing problem. Then, an agent is designed to learn edge selection for constructing the Multi-Layer Obstacle-Avoiding Steiner Tree (ML-OAST) using Double Deep Q-Network (DDQN). Finally, a post-processing stage is applied to further shorten the total wirelength through fast pruning and local optimization. Experimental results demonstrate that the proposed algorithm achieves better wirelength quality compared to state-of-the-art heuristic algorithms. Additionally, an ablation study confirms the effectiveness of DDQN in routing optimization.

Continuous-flow microfluidic biochips (CFMBs) automatically execute various bioassays by precisely controlling the transport of fluid samples, which is driven by pressure delivered through fluidic ports. High-level synthesis, as an important stage in the design flow of CFMBs, generates binding and scheduling solutions whose quality directly affects the efficiency of the execution of bioassays. Existing high-level synthesis methods perform numerous transport tasks concurrently to increase efficiency. However, fluidic ports cannot be shared between concurrently executing transport tasks, resulting in a large number of fluidic ports introduced by existing methods. Increasing the number of fluidic ports undermines the integration, reduces the reliability, and increases the manufacturing cost. In this paper, we propose a port-driven high-level synthesis method based on integer linear programming (ILP) called SlimPort, integrating the optimization of fluidic port number into high-level synthesis, which has never been considered in prior work. Meanwhile, to ensure bioassay correctness, volume management between devices with a non-fixed input/output ratio is realized. Additionally, two acceleration strategies for ILP, scheduling constraint reduction and upper boundary estimation of fluidic port number, are proposed to improve the efficiency of SlimPort. Experimental results from multiple benchmarks demonstrate that SlimPort leads to high assay execution efficiency and a low number of fluidic ports.