Yanyang Wang

Prof. Dr. Yanyang Wang


Research Focus & Metrics

Academic Career Length

1Year (2026-Present)

(Calculated once Scilit publication data is synced: current year − year of first publication + 1)

Representative Publications

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20 October 2026 in Preprints.org
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WJWenxia Jia
Wenxia Jia
YWYanyang Wang
Yanyang Wang
Runtime adaptive FPGA execution is attractive for in-vehicle language models because the dominant bottleneck changes with context length, inference phase, and memory pressure. This work develops a ZCU102/XCZU9EG-oriented architecture with four constant-budget modes that redistribute 2,048 DSPs between attention and feed-forward processing under a stateful break-even controller. Evaluation combines checkpoint-level W8A8 screening, benchmark-derived automotive request statistics, analytical and event models, and Monte Carlo controller experiments. For SmolLM2-135M-Instruct, W8A8 screening increases WikiText-2 perplexity by 2.95%; 390,510 STRIDE-QA human turns have a median length of 14 tokens and p95 of 48. The compute model predicts an attention-heavy-mode benefit of 22.01% at 8,192 tokens. Across twenty independent 1,000-request traces per workload, the controller reduces mean modeled request latency by 1.68% for routine traffic, 16.75% for multimodal traffic, and 17.49% for long-context bursts relative to static C0. Executed W8A8 operator tests report 1.38–1.77% normalized RMSE and cosine similarity above 0.99984. These results support context-aware, transition-cost-aware resource allocation for adaptive edge language-model acceleration.