Implantable bioelectronic devices for the simulation of peripheral nerves could be used to treat disorders that are resistant to traditional pharmacological therapies. However, for many nerve targets, this requires invasive surgeries and the implantation of bulky devices (about a few centimetres in at least one dimension). Here we report the design and in vivo proof-of-concept testing of an endovascular wireless and battery-free millimetric implant for the stimulation of specific peripheral nerves that are difficult to reach via traditional surgeries. The device can be delivered through a percutaneous catheter and leverages magnetoelectric materials to receive data and power through tissue via a digitally programmable 1 mm × 0.8 mm system-on-a-chip. Implantation of the device directly on top of the sciatic nerve in rats and near a femoral artery in pigs (with a stimulation lead introduced into a blood vessel through a catheter) allowed for wireless stimulation of the animals’ sciatic and femoral nerves. Minimally invasive magnetoelectric implants may allow for the stimulation of nerves without the need for open surgery or the implantation of battery-powered pulse generators.

While the move to smaller transistors has been a boon for performance it has dramatically increased the cost to fabricate chips using those smaller transistors. This forces the vast majority of chip design companies to trust a third party -- often overseas -- to fabricate their design. To guard against shipping chips with errors (intentional or otherwise) chip design companies rely on post-fabrication testing. Unfortunately, this type of testing leaves the door open to malicious modifications since attackers can craft attack triggers requiring a sequence of unlikely events, which will never be encountered by even the most diligent tester. In this paper, we show how a fabrication-time attacker can leverage analog circuits to create a hardware attack that is small (i.e., requires as little as one gate) and stealthy (i.e., requires an unlikely trigger sequence before effecting a chip's functionality). In the open spaces of an already placed and routed design, we construct a circuit that uses capacitors to siphon charge from nearby wires as they transition between digital values. When the capacitors fully charge, they deploy an attack that forces a victim flip-flop to a desired value. We weaponize this attack into a remotely-controllable privilege escalation by attaching the capacitor to a wire controllable and by selecting a victim flip-flop that holds the privilege bit for our processor. We implement this attack in an OR1200 processor and fabricate a chip. Experimental results show that our attacks work, show that our attacks elude activation by a diverse set of benchmarks, and suggest that our attacks evade known defenses.

Miniature wireless bioelectronic implants that can operate for extended periods of time can transform how we treat disorders by acting rapidly on precise nerves and organs in a way that drugs cannot. To reach this goal, materials and methods are needed to wirelessly transfer energy through the body or harvest energy from the body itself. We review some of the capabilities of emerging energy transfer methods to identify the performance envelope for existing technology and discover where opportunities lie to improve how much—and how efficiently—we can deliver energy to the tiny bioelectronic implants that can support emerging medical technologies.

A compact, accurate, and bitwidth-programmable in-memory computing (IMC) static random-access memory (SRAM) macro, named CAP-RAM, is presented for energy-efficient convolutional neural network (CNN) inference. It leverages a novel charge-domain multiply-and-accumulate (MAC) mechanism and circuitry to achieve superior linearity under process variations compared to conventional IMC designs. The adopted semi-parallel architecture efficiently stores filters from multiple CNN layers by sharing eight standard 6T SRAM cells with one charge-domain MAC circuit. Moreover, up to six levels of bit-width of weights with two encoding schemes and eight levels of input activations are supported. A 7-bit charge-injection SAR (ciSAR) analog-to-digital converter (ADC) getting rid of sample and hold (S&H) and input/reference buffers further improves the overall energy efficiency and throughput. A 65-nm prototype validates the excellent linearity and computing accuracy of CAP-RAM. A single $512\times 128$ macro stores a complete pruned and quantized CNN model to achieve 98.8% inference accuracy on the MNIST data set and 89.0% on the CIFAR-10 data set, with a 573.4-giga operations per second (GOPS) peak throughput and a 49.4-tera operations per second (TOPS)/W energy efficiency.

This paper presents an all-digital true random number generator (TRNG) harvesting entropy from the collapse of two edges injected into one even-stage ring, fabricated in 40 and 180 nm CMOS technologies. A configurable ring and tuning loop provides robustness across a wide range of temperature (-40°C to 120 °C), voltage (0.6 to 0.9 V), process variation, and external attack. The dynamic tuning loop automatically configures the ring to meet a sufficient collapse time, thereby maximizing entropy. Measured random bits pass all NIST randomness tests across all measured operating conditions and power supply attacks. In 40 nm, the TRNG occupies only 836μm ² and consumes 23 pJ/bit at nominal 0.9 V and 11 pJ/bit at 0.6 V.