In this paper, we present measurement results from a prototype chip (fabricated in 130 nm CMOS technology), designed to extract maximum power from a Thermoelectric Generator (TEG). From analytical expression, we prove that the maximum extracted power is around 75% of the available power in a TEG, without using a closed loop maximum peak power tracking to regulate the input voltage. In our measurements, the TEG is modeled by a voltage source (50mV-200mV) with a series resistance of 5 Ohms. The prototype is fully electric, starts from 50 mV and can extract 60% (at 50 mV) to 65% (at 200 mV) of the available power. Hence the measurement result closely agrees with the analytical expression.

This paper presents 2D-Sentaurus TCAD tool results of a Non-aligned Double Gate Junction N-Channel Field Effect Transistor (NADGNFET) device, the response analysis of device to gate oxide dielectric materials i.e. silicon dioxide (SiO₂) and hafnium dioxide (HfO₂) is also presented. The NADGNFET in 90 nm device length is the proposal of this work to improve the second order effects as well transistor non-linear performance at Radio Frequency (RF). A non-aligned device in this work consists of two gates extending to the source and drain region with 44.44% channel overlap in total device length. As compared to a full overlap device, the present device has shown better results in Analog Figure of Merit (FOM) and RF parameters like: I_ON current, I_ON/I_OFF ratio, DIBL (Drain Induced Barrier lowering), SS (Subthreshold Swing), Intrinsic gain (A_VO), Transconductance Generation Factor (TGF), Transconductance Frequency Product (TFP), Cut-off frequency (f_T), Intercepted Input Power-3 (IIP3), and Intermodulation Distortion power-3 (IMD3). The use of dielectric material with high dielectric constant (HfO₂, k=24) in gate oxide reduces DIBL by 50%, increases the I_ON/I_OFF ratio by 59.1%, increases the Intrinsic gain by 50% compared to low-k dielectric constant (SiO₂, k=3.9). However, results also shows that high frequency parameters results were better with low-k dielectric constant. This gives a trade-off in device application.

The present work gives an overview of a new device model named, NADGFETs (Non-Aligned Double Gate Field Effect Transistors) structure. The simulations were performed using the 2D-Sentaurus TCAD. The parameters of NADGNFET and NADGPFET namely threshold voltage, Drain Induced Barrier Lowering (DIBL), subthreshold swing (SS), ON current (I ON ), I ON /I OFF ratio, Intrinsic gain (Avo), Transconductance $(\mathrm{g}_{\mathrm{m}})$, and output conductance $(\mathrm{g}_{\mathrm{ds}})$, are being investigated. An inverter is simulated using the NADGFET devices giving a propagation delay of 37.5 $\mu\sec$ and a total power consumption of 3.5 nW.