For phased array receivers, mutual coupling leads to beam-dependent active impedances which must be taken into account when matching the array ports to front end amplifiers for optimal noise performance. We study the noise penalty for several noise matching conditions and develop a matching condition that minimizes the average beam equivalent receiver noise temperature over multiple beams. For non-beamforming applications such as multiple input multiple output communications, we show that noise performance for coupled arrays can be quantified using the spectrum of an equivalent receiver noise temperature correlation matrix.

This paper discusses noise figure optimization techniques for inductively degenerated cascode CMOS low-noise amplifiers (LNAs) with on-chip gate inductors. Seven different optimizations techniques are discussed. Of these, five new cases provide power match and balance the transistor noise contribution and the noise contribution from all parasitic resistances in the gate circuit to achieve the best noise performance under the constraints of integrated gate inductor quality factor, power consumption, and gain. Three of the power matched techniques (two power constrained optimizations and a gain-and-power constrained optimization) are recommended as design strategies. These three optimization techniques significantly improve the noise figures for LNA designs that are to employ on-chip gate inductors.

This study presents new techniques for implementing continuous-time second-order band-pass filters with high-quality factors and asymmetric slopes. The techniques are centred around the realisation of two non-conventional transfer functions which include the non-integer-order Laplacian operator s^α; 0<α<1. Four main possible circuit realisations; one based on a frequency-dependent negative resistor (FDNR), another based on an inductor and two based on multiple amplifier biquads (MABs) are given and verified using Spice and experimentally for both transfer functions. In addition, a field programmable analogue array (FPAA) realisation is tested and verified. Last but not least, a possible realisation using current conveyors is also given, tested and verified.

This paper discusses the design of a monolithic microwave integrated circuit (MMIC) class-J GaN power amplifier (PA). Theoretical derivations of optimum load impedances, output power, and efficiency are presented to demonstrate their dependence on the quality factor of the integrated inductor used in the output matching network. A group of design curves are obtained to select the optimum transistor size and impedance according to the required output power and efficiency for a given inductor loss. An analytical-based design methodology using the design curves is proposed. To verify the accuracy of this analytical design approach, an integrated 0.5-W 15-V monolithic microwave integrated circuit PA is fabricated in 0.8- $\mu$m GaN technology. The PA exhibits greater than 50% drain efficiency over 825 MHz, from 2.25 to 3.075$~$GHz.

A continuous-time (CT) radio frequency (RF) antenna array beamformer and analog circuit based on a discrete-space-continuous-time (DSCT) 2-D fan-filter having transfer function H_F,A(z_x,s_ct) is derived. The proposed transfer function is based on a 2-D FIR discrete domain fan filter. The discrete domain prototype is converted to the proposed mixed-domain DSCT analog filter by replacing unit sampled delays with CT analog first-order all-pass networks corresponding to the bilinear transform. First-order all-pass network Φ(s_t) is a poor approximation to a CT delay exp(-sT) . To address this, a novel broadband pre-warping method is proposed to exactly compensate for such “bilinear warping”. A 65 nm CMOS VLSI circuit for Φ(s_t) is proposed and an example fan filter with axis oriented at θ₀=35^°, half-fan-angle ε = 5^° and maximum frequency F_u = 2.6 GHz is simulated employing closed-form expressions, an ABCD parameter based model and 65 nm CMOS simulations in Cadence. A stop-band interference rejection of 38 dB is verified by BSIM4 based simulations. The proposed circuit for Φ(s_t) operates at 3.7 mA from a 1.2 V supply. The beamfomer is shown to operate correctly in the presence of PVT variations of Φ(s_t).

This paper presents an inductorless 0.13- μm CMOS TIA structure that is a modified version of a regulated cascode (RGC) TIA. An immittance converter is incorporated to reduce power consumption while increasing transimpedance gain. Measured 3-dB bandwidth is 7 GHz, sufficient for 10-Gb/s operation, in the presence of 250 fF capacitance at the TIA input, representative of typical CMOS photodiode capacitance. The transimpedance gain of the single-stage TIA is 50 dBΩ, and the group-delay variation is less than ±19 ps over the 3-dB bandwidth. The circuit occupies an active area of 180 μm×90 μm and consumes 7 mW from a 1.5-V supply. The measured average input-referred current noise of the TIA is 31 pA/√{Hz}. Simulations and analysis show that the proposed single-stage TIA architecture is capable of achieving improvement in the transimpedance limit over a single-stage RGC TIA designed for the same data rate and the same input photodiode capacitance. A comparison of measurement results to published TIAs also demonstrates the competitive performance of the proposed TIA in terms of the TIA transimpendance gain, bandwidth, area, and power consumption.