Heavy ion data suggest that a common mechanism is responsible for single-event burnout in 1200 V power MOSFETs and junction barrier Schottky diodes. Similarly, heavy ion data suggest a common mechanism is also responsible for leakage current degradation in both devices. This mechanism, based on ion-induced, highlylocalized energy pulses, is demonstrated in simulations and shown to be capable of causing degradation and singleevent burnout for both the MOSFETs and JBS diodes.

Cross sections and failure in time rates for neutron-induced single-event burnout (SEB) are estimated for SiC power MOSFETs using a method based on combining results from heavy ion SEB experimental data, 3-D TCAD prediction of sensitive volumes, and Monte Carlo radiation transport simulations of secondary particle production. The results agree well with experimental data and are useful in understanding the mechanisms for neutron-induced SEB data.

Silicon carbide (SiC) power metal-oxide-semiconductor field effect transistors (MOSFETs) are space-ready in terms of typical reliability measures. However, single event burnout (SEB) due to heavy-ion irradiation often occurs at voltages 50% or lower than specified breakdown. Failure rates in space are estimated for burnout of 1200 V devices based on the experimental data for burnout and the expected heavy-ion linear energy transfer (LET) spectrum in space.

The ever-decreasing charge required to represent a logic HIGH state at a circuit node has resulted in increased vulnerability of advanced ICs to Single-Event Upsets. Design approaches that address this threat to reliable operation of ICs are needed. The approach presented here uses logical masking through approximate functions to reduce the single-event error rate of a given circuit. Results on benchmark circuits show the effectiveness of this approach for mitigating the threat of SEU's

A combination of commercial simulation tools and custom applications utilizing Geant4 physics libraries is used to analyze thermal neutron induced soft error rates in a commercial bulk CMOS SRAM. Detailed descriptions of the sensitive regions based upon technology in computer-aided design calibration are used in conjunction with a physics-based Monte Carlo simulator to predict neutron soft error cross sections that are in good agreement with experimental results

Bulk and silicon-on-insulator (SOI) n-channel FinFETs with fin widths of 15–40 nm and channel lengths of 45 and 1000 nm were irradiated with 1.8 MeV protons at temperatures of 295 and 90 K. Bulk and SOI FinFETs show improved transconductance and steeper subthreshold slopes before irradiation at 90 K than at 295 K. Increased off-state leakage currents are observed for longer channel bulk FinFETs for doses above 300–500 krad (SiO ₂ ) for 295 and 90 K irradiation, and at lower doses for shorter channel devices. Threshold-voltage shifts for irradiation up to 1 Mrad(SiO ₂ ) are greater for SOI devices at 90 K than at 295 K due to enhanced charge trapping in the buried oxide (BOX). TCAD simulations provide insight into radiation-induced trapped-charge densities in the SOI devices.