Accurate retail demand forecasting is integral to the operational efficiency of any retail business. As demand is described over time, the prediction of demand is a time-series forecasting problem which may be addressed in a univariate manner, via statistical methods and simplistic machine learning approaches, or in a multivariate fashion using generic deep learning forecasters that are well-established in other fields. This study analyzes, optimizes, trains and tests such forecasters, namely the Temporal Fusion Transformer and the Temporal Convolutional Network, alongside the recently proposed Time-Series Mixer, to accurately forecast retail demand given a dataset of historical sales in 45 stores with their accompanied features. Moreover, the present work proposes a novel extension of the Time-Series Mixer architecture, the LSTMixer, which utilizes an additional Long Short-Term Memory block to achieve better forecasts. The results indicate that the proposed LSTMixer model is the better predictor, whilst all the other aforementioned models outperform the common statistical and machine learning methods. An ablation test is also performed to ensure that the extension within the LSTMixer design is responsible for the improved results. The findings promote the use of deep learning models for retail demand forecasting problems and establish LSTMixer as a viable and efficient option.

A low complexity MIMO Volterra Decision Feedback Equalizers (VDFE) for optical transmission systems employing NRZ-DQPSK signalling is proposed. Based on a comparative study performed by means of simulations, it is proved that the proposed equalizers maintain the required efficiency in terms of BER, achieving significant reduction in terms of complexity. Also, suitable architectures for high-speed FPGA implementations are presented. A 8-input 2-output low complexity VDFE involving three taps feed-forward filtering and two taps backward filtering was implemented on a single state-of-the-art FPGA. The target rate of 40 Gb/s is achieved by applying extensive pipelining and parallelism and fully exploiting specific FPGA features.