We present an analog-integrated circuit implementation of long short-term memory network, which is compatible with digital CMOS technology. We have used multiple-input floating gate MOSFETs as both the front-end to obtain converted analog signals and the differential pairs in proposed analog multipliers. Analog crossbar is built by the analog multiplier processing matrix and bitwise multiplications. We have shown that using current signals as internal transmission signals can largely reduce computation delay, compared to the digital implementation. We also have introduced analog blocks to work as activation functions for the algorithm. In the back-end of our design, we have used current comparators to achieve the output to be readable to external digital systems. We have designed the LSTM network with the matrix size of 16 × 16 in TSMC 180nm CMOS technology. The post-layout simulations show that the latency of one computing cycle is 1.19ns without memory, and power dissipation of the single analog LSTM computing core with 2 kilobytes SRAM at 200MHz is 460.3mW. The overhead of power dissipation due to SRAM access is 8.3%, in which the computing of each LSTM layer requires one computing cycle. The energy efficiency is 0.95TOP/s/W.

In this paper, we present a physics-based analytical model of GNR FET, which allows for the evaluation of GNR FET performance including the effects of line-edge roughness as its practical specific non-ideality. The line-edge roughness is modeled in edge-enhanced band-to-band-tunneling and localization regimes, and then verified for various roughness amplitudes. Corresponding to these two regimes, the off-current is initially increased, then decreased; while, on the other hand, the on-current is continuously decreased by increasing the roughness amplitude.