In this work, we study the high critical breakdown field in β-Ga₂O₃ perpendicular to its (100) crystal plane using a β-Ga₂O₃/graphene vertical heterostructure. Measurements indicate a record breakdown field of 5.2 MV/cm perpendicular to the (100) plane that is significantly larger than the previously reported values on lateral β-Ga₂O₃ field-effect-transistors (FETs). This result is compared with the critical field typically measured within the (100) crystal plane, and the observed anisotropy is explained through a combined theoretical and experimental analysis.

This paper provides comprehensive experimental analysis relating to improvements in the two-dimensional (2D) p-type metal–oxide–semiconductor (PMOS) field effect transistors (FETs) by pure van der Waals (vdW) contacts on few-layer tungsten diselenide (WSe₂) with high-k metal gate (HKMG) stacks. Our analysis shows that standard metallization techniques (e.g., e-beam evaporation at moderate pressure ~ 10^–5 torr) results in significant Fermi-level pinning, but Schottky barrier heights (SBH) remain small (< 100 meV) when using high work function metals (e.g., Pt or Pd). Temperature-dependent analysis uncovers a more dominant contribution to contact resistance from the channel access region and confirms significant improvement through less damaging metallization techniques (i.e., reduced scattering) combined with strongly scaled HKMG stacks (enhanced carrier density). A clean contact/channel interface is achieved through high-vacuum evaporation and temperature-controlled stepped deposition providing large improvements in contact resistance. Our study reports low contact resistance of 5.7 kΩ-µm, with on-state currents of ~ 97 µA/µm and subthreshold swing of ~ 140 mV/dec in FETs with channel lengths of 400 nm. Furthermore, theoretical analysis using a Landauer transport ballistic model for WSe₂ SB-FETs elucidates the prospects of nanoscale 2D PMOS FETs indicating high-performance (excellent on-state current vs subthreshold swing benchmarks) towards the ultimate CMOS scaling limit.

Recent studies of resistive switching devices with hexagonal boron nitride (h-BN) as the switching layer have shown the potential of two-dimensional (2D) materials for memory and neuromorphic computing applications. The use of 2D materials allows scaling the resistive switching layer thickness to sub-nanometer dimensions enabling devices to operate with low switching voltages and high programming speeds, offering large improvements in efficiency and performance as well as ultra-dense integration. These characteristics are of interest for the implementation of neuromorphic computing and machine learning hardware based on memristor crossbars. However, existing demonstrations of h-BN memristors focus on single isolated device switching properties and lack attention to fundamental machine learning functions. This paper demonstrates the hardware implementation of dot product operations, a basic analog function ubiquitous in machine learning, using h-BN memristor arrays. Moreover, we demonstrate the hardware implementation of a linear regression algorithm on h-BN memristor arrays.

Focus in deep neural network hardware research for reducing latencies of memory fetches has steered in the direction of analog-based artificial neural networks (ANN). The promise of decreased latencies, increased computational parallelism, and higher storage densities with crossbar non-volatile memory (NVM) based in-memory-computing/processing-in-memory techniques is not without its caveats. This paper surveys this rich landscape and highlights the advantages and challenges of emerging NVMs as multi-level synaptic emulators in various neural network types and applications. Current and potential methods for reliably programming these devices in a crossbar matrix are discussed, as well as techniques for reliably integrating and propagating matrix products to emulate the well-known MAC-like operations throughout the neural network. This paper complements previous surveys, but most importantly uncovers further areas of ongoing research relating to the viability of analog-based ANN implementations based on state-of-the-art NVM technologies in the context of hardware accelerators. While many previous reviews of analog-based ANN focus on device characteristics, this review presents the perspective of crossbar arrays, peripheral circuitry and the required architectural and system considerations for an emerging memory crossbar neural network.