An innovative laboratory methodology for an introductory digital design course is presented. Instead of having traditional lab experiences, where students have to come to school classrooms, a ldquolab at homerdquo concept is proposed. Students perform real experiments in their own homes, using hardware kits specially developed for this purpose. They analyze given problems, design the appropriate solutions, and test the actual circuit in a distance learning context. Four course offerings were successfully accomplished with this methodology, and more than 65 kits with a programmable logic board were given to groups of students for the whole semester in each of these. An opinion survey showed that the experience was very successful among students. Laboratory learning objectives are analyzed to validate this experience. This paper also discusses scalability and different students' work evaluation approaches, in order to facilitate the application of this methodology to other contexts. Moreover, the ldquolab at homerdquo is shown to be very suitable for high enrollment courses and easy to scale, providing actual hardware platforms for students at an affordable cost for the institution.

This work presents a wireless multichannel electroencephalogram (EEG) recording system featuring lossless and near-lossless compression of the digitized EEG signal. Two novel, low-complexity, efficient compression algorithms were developed and tested in a low-power platform. The algorithms were tested on six public EEG databases comparing favorably with the best compression rates reported up to date in the literature. In its lossless mode, the platform is capable of encoding and transmitting 59-channel EEG signals, sampled at 500 Hz and 16 bits per sample, at a current consumption of 337 $\mu$A per channel; this comes with a guarantee that the decompressed signal is identical to the sampled one. The near-lossless mode allows for significant energy savings and/or higher throughputs in exchange for a small guaranteed maximum per-sample distortion in the recovered signal. Finally, we address the tradeoff between computation cost and transmission savings by evaluating three alternatives: sending raw data, or encoding with one of two compression algorithms that differ in complexity and compression performance. We observe that the higher the throughput (number of channels and sampling rate) the larger the benefits obtained from compression.

This paper presents experimental measurements of power consumption using different techniques to turn off part of a system and switch between active and standby modes. The main ideas analyzed are: clock gating, clock enable, and blocking inputs. The laboratory work is described, including the measurement setups and the benchmark circuits. Quantitative measurements in both a 65 nm CMOS Cyclone III and a 45 nm CMOS Spartan 6 FPGAs are presented. The selected circuits used as benchmarks are different type of multipliers. Results of power consumption in active and standby modes are presented and compared.

This work reviews the contributions of power-oriented pipelining over the last two decades, and adds up-to-date results on 65 nm and 45 nm FPGAs. The data show that power consumption can be reduced by a factor between 0.1 and 0.8 using different levels of pipelining. More than 34 experiments, developed in 12 laboratories in 8 countries during 17 years are summarized. This paper also contributes to this research topic adding updated results for Altera 65 nm Cyclone III and Xilinx 45 nm Spartan-6 devices.

This work presents a wearable multi-channel EEG recording system featuring a lossless compression algorithm. The algorithm, based in a previously reported algorithm by the authors, exploits the existing temporal correlation between samples at different sampling times, and the spatial correlation between different electrodes across the scalp. The low-power platform is able to compress, by a factor between 2.3 and 3.6, up to 300sps from 64 channels with a power consumption of 176μW/ch. The performance of the algorithm compares favorably with the best compression rates reported up to date in the literature.

This paper presents experimental measurements of power consumption for core logic of a 65-nm Cyclone III FPGA and its comparison with the value predicted by the power estimation tool. The laboratory work is described, including the measurement setup, the benchmark circuits, and the CAD flows utilized to obtain power estimations. The selected circuits used as benchmarks were different type of multipliers implemented in LUTs and in embedded blocks both with or without pipelining stages. Three type of results are presented: first, the error between power measurements and power estimations; second, the power savings by using pipeline stages, and third, the quantification of power savings by using embedded blocks.