Implantable neural interfacing devices have added significantly to neural engineering by introducing the low-frequency oscillations of small populations of neurons known as local field potential as well as high-frequency action potentials of individual neurons. Regardless of the astounding progression as of late, conventional neural modulating system is still incapable to achieve the desired chronic in vivo implantation. The real constraint emerges from mechanical and physical differences between implants and brain tissue that initiates an inflammatory reaction and glial scar formation that reduces the recording and stimulation quality. Furthermore, traditional strategies consisting of rigid and tethered neural devices cause substantial tissue damage and impede the natural behavior of an animal, thus hindering chronic in vivo measurements. Therefore, enabling fully implantable neural devices requires biocompatibility, wireless power/data capability, biointegration using thin and flexible electronics, and chronic recording properties. This article reviews biocompatibility and design approaches for developing biointegrated and wirelessly powered implantable neural devices in animals aimed at long-term neural interfacing and outlines current challenges toward developing the next generation of implantable neural devices.

We propose FinFETs with unequal source and drain doping concentrations [asymmetrically doped (AD) FinFETs] for low-power robust SRAMs. The effect of asymmetric source/drain doping on the device characteristics is extensively analyzed, and the key differences between conventional and AD FinFETs are clearly shown. We show that asymmetry in the device structure leads to unequal currents for positive and negative drain biases, which is exploited to achieve mitigation of read-write conflict in 6T SRAMs. The proposed device exhibits superior short-channel characteristics compared to a conventional FinFET due to reduced electric fields from the terminal that has a lower doping. This results in significantly lower cell leakage in AD-FinFET-based 6T SRAM. Compared to the conventional FinFET-based 6T SRAM, AD-FinFET SRAM shows 5.2%-8.3% improvement in read static noise margin (SNM), 4.1%-10.2% higher write margin, 4.1%-8.8% lower write time, 1.3%-3.5% higher hold SNM, and 2.1-2.5 lower cell leakage at the cost of 20%-23% higher access time. There is no area penalty associated with the proposed technique.

This paper presents a low-power high-input-impedance analog-front-end (AFE) design including an instrumentational-amplifier (IA) and a neural-signal-specific ADC (NSS-ADC) for continuous acquisition of electroencephalography (EEG) signals. In the proposed AFE, low-voltage low-power design techniques are used to reduce the power consumption of the whole system. Furthermore, by utilizing the proposed NSS-ADC, high-amplitude EEG spikes, which convey more important information, are converted with higher resolutions, while the background-noise (B-Noise) of the EEG signal is converted with the lowest resolution. Hence, when the NSS-ADC enters the inactive region, the resolution- and DAC- controlling-units (RCU and DCU) set the analog and digital components of the NSS-ADC into off mode, which leads to power reduction. Based on measurement results, the AFE consumes a power of 3.7 μW under the sampling rate of 20 KS/s. In the proposed AFE, to avoid signal attenuation, active-electrodes (AEs) are utilized to enhance the input impedance of the AFE up to 102 GΩ and 5.2 GΩ at 1 Hz and 20 Hz, respectively. In addition, by using circuit-design techniques the input-referred-noise is reduced as low as 1.5 μV $_\text{rms}$ over 0.5-1.2 kHz. Finally, by using a transconductance-driven-right-leg (TDRL) and a common-mode-feedback (CMFB) blocks, a common-mode-rejection-ratio (CMRR) of 108 dB is achieved.

With the fast progress in miniaturization of sensors and advances in micromachinery systems, a gate has been opened to the researchers to develop extremely small wearable/implantable microsystems for different applications. However, these devices are reaching not to a physical limit but a power limit, which is a critical limit for further miniaturization to develop smaller and smarter wearable/implantable devices (WIDs), especially for multi-task continuous computing purposes. Developing smaller and smarter devices with more functionality requires larger batteries, which are currently the main power provider for such devices. However, batteries have a fixed energy density, limited lifetime and chemical side effect plus the fact that the total size of the WID is dominated by the battery size. These issues make the design very challenging or even impossible. A promising solution is to design batteryless WIDs scavenging energy from human or environment including but not limited to temperature variations through thermoelectric generator (TEG) devices, body movement through Piezoelectric devices, solar energy through miniature solar cells, radio-frequency (RF) harvesting through antenna etc. However, the energy provided by each of these harvesting mechanisms is very limited and thus cannot be used for complex tasks. Therefore, a more comprehensive solution is the use of different harvesting mechanisms on a single platform providing enough energy for more complex tasks without the need of batteries. In addition to this, complex tasks can be done by designing Integrated Circuits (ICs), as the main core and the most power consuming component of any WID, in an extremely low power mode by lowering the supply voltage utilizing low-voltage design techniques. Having the ICs operational at very low voltages, will enable designing battery-less WIDs for complex tasks, which will be discussed in details throughout this paper. In this paper, a path towards battery-less computing is drawn by looking at device circuit co-design for future system-on-chips (SoCs).

In this paper, FinFET devices are compared to bulk CMOS technology by looking at the characteristics of both devices and their challenges in nano-scale regimes. The effects of process variations on these devices along with the effect of device parameters on their characteristics are explored. Both FinFET and CMOS devices are used in 6T and 8T-SRAM cells. Simulation results show significant improvements for FinFET-based SRAMs compared to bulk CMOS-based SRAM cells. FinFET based 6T-SRAM cell shows 39% improvement in read static noise margin, 54% higher write margin, 54% smaller minimum supply voltage applicable, and 7.3X less leakage power compared to its CMOS counterpart. 8T-SRAM using FinFET improved read static noise margin, write margin, minimum supply voltage and leakage power consumption by 7%, 64%, 50%, and 3.1X compared to bulk-CMOS 8T-SRAM, respectively.