FeFETs with 5-nm-thick Hf0.5Zr0.5O2 (HZO) have been demonstrated in memory operations for the ON/OFF current ratio >104 at zero gate voltage and an MW (memory window) of 0.6-0.7 V. A gradual transition of the ferroelectricity with an increasing crystallization temperature for the gate-last process was presented. The excellent program/erase (P/E) data retention are the ~2x104 ON/OFF ratio and 0.67 V extrapolated to 10 years with VP/E=±b4.8 V. The MW remains >0.2 V after 106 cycles for read and vanishes with cycles of 103-104 for write, which is the bottleneck for ferroelectric-type memories. The mechanism of retention and endurance are discussed. The characteristic of this work is an unaffected coercive-field (~1 MV/cm) with scaling FE-HZO down to 5-nm-thick, which is beneficial for reducing the operation voltage. Comparable performance with previous works on high data retention and endurance with low voltage for read are achieved. The ultrathin ferroelectric layer proposes a realistic emerging memory for 1T architecture.

A double-HZO (HfZrO ₂ ) FeFET (ferroelectric FET) with nonidentical ferroelectric thicknesses is experimentally demonstrated with as low as |V _P/E | = 5 V, 2-bit endurance > 10 ⁵ cycles and retention > 10 ⁴ s. Inserting an insulator to separate the ferroelectric layers and avoid the monoclinic formation of a thick Fe-HZO (ferroelectric-HZO) is a useful method to enhance the MW (memory window) for MLC (multilevel cell) applications. Double-HZO has a lower ER (error rate) and shows a 600X improvement compared to single-HZO. The stacked HZO FeFET has potential as an MLC for high-density NVM (nonvolatile memory) applications.

Atomic layer deposition (ALD)-based TiN electrode on ferroelectric HfZrO₂ metal/ferroelectric/metal (MFM) capacitor and ferroelectric field-effect transistor (FeFET) is demonstrated experimentally with weight transfer, that is, Δ P, per pulse analysis through consecutive alternating potentiation/depression (Pot./Dep.) training pulses. The weight training pulse schemes are studied to have symmetric and linear synapse weight transfer to increase the accuracy and accelerate the deep neural network (DNN) training. With ALD TiN inserted, αp/αd = -0.63/-0.84, asymmetry |αp - αd| = 0.21, and polarization modulation ratio (Pot./Dep.) = 97%/98% are achieved for MFM capacitor, and αp/αd = -1.32/-1.88, asymmetry |αp - αd| = 0.56, and Gmax/Gmin > 10x are delivered for FeFET.

The bilayer-based Antiferroelectric Tunneling Junction (AFTJ) with ferroelectric (FE) HfZrO ₂ (HZO) and dielectric (DE) Al ₂ O ₃ demonstrates a current ratio of $> 100\times $ , a TER (tunneling electroresistance) of $> 50\times $ , multilevel states, $> 10^{4}$ sec retention, and a cycling endurance as high as 10 ⁸ . The concept of tunneling current through DE in an antiferroelectric (AFE) system enhances the capacity to modulate the current/TER ratio and makes the AFTJ feasible for low-power crossbar eNVM (embedded nonvolatile memory) applications.

The concept of ferroelectric (FE) negative capacitance (NC) may be a turning point in overcoming the physical limitations imposed by the Boltzmann tyranny to realize next-generation state-of-the-art devices. Both the body factor (m-factor) and the transport mechanism (n-factor) are simultaneously improved by integrating an NC with a tunnel FET (TFET). The modeling approach is discussed in this study as well as the NC physics. By optimizing the thicknesses of FE, semiconductor, and interfacial layers, the capacitance of the FE layers is modulated to match that of a MOS resulting in the smallest subthreshold swing that is also hysteresis-free. An ultrathin-body double gate tunnel FET (UTB-DG-TFET) exhibits a steep slope (a subthreshold swing below 10 mV/dec over more than 4 orders of magnitude) for low-power applications (<0.2 V switching voltage) to realize next-generation state-of-the-art devices.