A BJT-based CMOS temperature sensor with an extremely wide temperature range is presented. A voltage mode read-out circuit structure based on common-mode temperature drift suppression technique is proposed to reduce the error caused by the high temperature drift of the read-out circuit in the CMOS process. By analyzing the ratiometric measurement scheme of the temperature sensor, a high sensitivity and high linearity common-mode temperature suppression structure is proposed to ensure the regular operation of the read-out circuit. It makes the structure more robust and expandable, and is suitable for the voltage domain temperature sensor read-out systems. The prototype of the sensor, implemented in a 180nm CMOS process, shows a measured inaccuracy within ±1C(3σ) from.40C to 175C with 1-point calibration and temperature sensing ultra-linearity R2 is more significant than 0.99. It occupies a die area of 0.42mm2 and consumes 0.3 mW with a medium resolution 12 bit and a fast conversion time of 10 μs.

The accuracy of estimating lithium battery internal parameters and state of charge (SOC) is closely related to the appropriate model and efficient algorithm. The real-time online estimation of the open-circuit voltage (OCV) model and the model parameters for multiple time scales are particularly significant. This article proposes an online dual time-scale recursive least squares (DTRLS) for closed-loop estimation of resistor–capacitor ( $RC$ ) network parameters, OCV, and SOC of equivalent circuit model (ECM). The dynamic characteristics of the battery system are analyzed at multiple time scales. The model parameters are separated and decoupled to overcome the parameter deviation and numerical issue in the time domain of the classical recursive least squares (RLS) method. In the slow time scale, the OCV parameter is coestimated without additional offline open-loop tests to improve the accuracy of SOC. Under the Urban Dynamometer Driving Schedule (UDDS) test, the ECM parameters and terminal voltages estimated by the proposed DTRLS method are compared with that of classical forgetting factor RLS (FFRLS). The root-mean-squared error (RMSE) results show that the online closed-loop DTRLS method improves the estimation accuracy of terminal voltage, OCV, and SOC by 0.97%, 3.2%, and 2.06%, respectively.

Efficient battery management system (BMS) monitoring and accurate battery state estimation are inseparable from precise battery models and model parameters. Because of the multi-time scale dynamic characteristics of the battery system, there are still challenges in the modeling and parameter identification accuracy of the battery equivalent circuit model (ECM) in this case. This paper proposes a multi-time scale parameter identification algorithm based on multi-resolution analysis (MRA) of discrete wavelet transform (DWT), which is used for closed-loop estimation of battery ECM parameters corresponding to different electrochemical dynamic effects. The ECM of the battery at multiple time scales is determined by the distribution of relaxation times (DRT) method, and MRA decomposition is performed on the battery signal to determine the separated and decoupled model parameters. The open circuit voltage (OCV) is used as a slow time scale model parameter and does not require offline state of charge (SOC)-OCV calibration. Under the urban dynamometer driving scheme (UDDS) experiment, the estimation results of ECM parameters, terminal voltage and SOC using the proposed algorithm were compared with those obtained using different implementation methods. The root mean square error (RMSE) results show that the algorithm can accurately estimate the terminal voltage, OCV and SOC of the battery, with estimation errors of 0.966mV,2.58mV, and 0.1263%, respectively.

The performance of the conventional Sigma-Delta modulator can be improved by cascading electrical integrator behind the mechanical sensing element. In this paper, a novel Sigma-Delta modulator with a fractional-order P I λ D μ controller is proposed and thus extending the traditional Sigma-Delta modulator to a new fractional-order in the Sigma-Delta ADC design field. The fractional-order P I λ D μ controller allows fine tuning accuracy in seeking the coefficients for the proposed Sigma-Delta modulator and provides the robust stability in the placement of poles and zeros for compensating the phase delays. The parameters of the proposed fractional-order Sigma-Delta modulator is designed by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance. Simulation from the proposed fractional-order Sigma-Delta modulator, results of SNR > 134 dB and the noise floor under –170 dB are obtained in frequency range of [5-150 Hz].

This paper proposes using a fractional‐order digital loop integrator to improve the robust stability of Sigma‐Delta modulator, thus extending the integer‐order Sigma‐Delta modulator to a non‐integer‐order (fractional‐order) one in the Sigma‐Delta ADC design field. The proposed fractional‐order Sigma‐Delta modulator has reasonable noise characteristics, dynamic range, and bandwidth; moreover the signal‐to‐noise ratio (SNR) is improved remarkably. In particular, a 2nd‐order digital loop integrator and a digitalPI^λD^μcontroller are combined to work as the fractional‐order digital loop integrator, which is realized using FPGA; this will reduce the ASIC analog circuit layout design and chip testing difficulties. The parameters of the proposed fractional‐order Sigma‐Delta modulator are tuned by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance. Simulation results are given and they demonstrate the efficiency of the proposed fractional‐order Sigma‐Delta modulator.