To guarantee system stability, proportional capacitor-current-feedback (CCF) active damping control has been widely used in LCL -type grid-connected inverter. However, when digital control is adopted in a grid-side current-controlled inverter, proportional CCF active damping will show negative damping characteristic in frequency band higher than one-sixth of the sampling frequency ( f _s /6), causing poor robustness in weak grid. In this article, an unstable second-order phase lead compensator is proposed to insert into the CCF path for eliminating the negative effect resulting from the digital control delay. In doing so, the positive damping region is extended to almost Nyquist frequency ( f _s /2), which achieves high robustness against grid impedance variation. To ensure system stability, the discrete rule is investigated for the proposed compensator and system performance is analyzed when the LCL resonance frequency changes in the range of (0, f _s /2) in discrete domain, a particularly simple and practical design is further presented for the proposed compensator and the current regulator. Finally, the effectiveness of the proposed strategy and parameters design is verified by the experimental results.

Limited by low availability, high price, and poor switching performance of high voltage power devices, connecting low voltage devices in series to block much higher voltages is always an option. However, severe voltage unbalance during turn-off transient remains to be solved. Most of existing methods designed for low speed Silicon (Si) IGBT cannot be directly transplanted to series-connected Silicon Carbide (SiC) MOSFETs with high switching speed. In order to maximum the switching performance of SiC MOSFETs, an elegant implementation of adjusting driving signals time delay method is proposed. In addition, a simplified model during drain-source voltage rising transient is discussed to basically reveal features and problems of series-connected SiC MOSFETs. Factors affecting the appropriate time delay are discussed as well, especially the influence of the load current. The simplified model and the implementation are both verified by experiments. Indeed, the proposed active voltage balancing control works well and has no penalty of sacrificing switching performance of SiC MOSFETs.

Phase-locked loop (PLL) with improper bandwidth could lead to potential instability issues for the grid-connected voltage source converters (VSCs) under weak grid conditions. The current loops of the VSCs can be designed faster as the development of the silicon carbide (SiC) and gallium nitride (GaN) semiconductor materials. It is questionable whether the PLL’s bandwidth could also be designed higher for faster current loop. Hence, the relationship between the bandwidth of the current loop and that of the PLL is studied first. It is revealed that the bandwidth of the PLL might not be increased linearly with the increasing of the bandwidth of the current loop, thus the traditional design principle, i.e. the bandwidth of the PLL is not higher than one-tenth of that of the current loop, might no longer be suitable. Thus, this paper proposes a design method of the PLL to make the grid-connected VSCs to have adequate stability margin and satisfactory dynamic performances under weak grid conditions. The current loop is deigned independently, while the PLL is designed considering the coupling between the current loop and the PLL under weak grid conditions. The simulations and experimental results verifies the theoretical analysis and the proposed design method.

Grid-side current control based on capacitor-current-feedback (CCF) active damping is a common control method for LCL -type grid-tied inverters. The control system should not only ensure inverter stability under complex grid conditions, but also be simple in structure. Therefore, the multiobjective design for the CCF control is proposed to enhance the passivity, while improving the internal stability. First, the passive constraint of CCF control is derived, from which two general control schemes, namely, negative CCF-based phase-lead (N-Lead) control scheme and positive CCF-based phase-lag (P-Lag) control scheme, are proposed. Then, the two schemes are implemented by the design of a first-order phase-lead CCF controller and a first-order phase-lag compensator-based positive CCF controller. Besides, the parameters design is also given for the convenience of engineering application. Finally, the experimental results verify the theoretical analysis and the effectiveness of the proposed design methods.

Modular multilevel converter with integrated battery energy storage system has been verified as a better choice for large-scale battery energy storage system. However, battery power and its unbalanced distribution in submodules lead to significant increase of capacitor voltage ripple. Larger submodule capacitance is required to maintain the ripple within reasonable limits, increasing the cost and volume of the system. To address the problem, this article proposes a novel battery integration method. Each battery pack is connected with two submodules that belong to upper and lower arm, respectively, through an isolated three-port dc-dc converter. The proposed method can ensure the power balance between upper and lower arm to eliminate fundamental circulating current and reduce capacitor voltage ripple. Three-port converters provide power channels for the fundamental power fluctuation of arms; thus, capacitor voltage ripple is further reduced. Then, the small-signal model of the proposed structure is built, and the control strategy is designed to realize both capacitor voltage ripple reduction and battery power control. Finally, a downscaled prototype is built and detailed experiment results verify the effectiveness of the proposed battery integration method and control strategy.

Modular multilevel converter with integrated battery energy storage system (MMC‐BESS) has been proposed for energy storage requirements in high‐voltage applications with large‐scale renewable energy resources. The MMC‐BESS is essentially a three‐port converter which can transfer energy between any two of the ac port, dc port, and BESS, constituting multimode operation of the system. Different from conventional MMCs, the state‐of‐charge (SOC) inconsistency among batteries would magnify the submodule capacitor voltage unbalance issue in the MMC‐BESS. In this study, an improved capacitor voltage balancing method applicable for multimode operation of MMC‐BESS is proposed by adjusting ac and dc modulation indexes simultaneously. After that, the ratio of ac and dc modulation indexes is optimised to enhance the tolerance of unbalanced power among SMs within phase arm, greatly improving the SOC equalisation rate. Based on the proposed capacitor voltage balancing method, the control structure is given and the dynamic model is conducted for the analytic design of the closed‐loop controller. Finally, the simulations and experimental results validate the effectiveness and feasibility of the proposed control strategy.