Current mode controls have been widely used in many power converters with various topologies. Small signal equivalent circuit model is an effective tool for controller design. However, no unified equivalent circuit model applicable to various converters is available. This paper proposes a unified three-terminal switch model for current mode controls with constant frequency and variable frequency modulations operating in continuous conduction mode, providing an accurate and simple equivalent circuit for various converters using current mode control schemes. By identifying the invariant three-terminal structure in current mode control pulsewidth modulation (PWM) converters, which consists of active switch, passive switch, inductor, and closed current loop, the terminal current and voltage relationships are studied and represented by a small signal equivalent circuit. A small signal model for a current mode control PWM converter can be obtained by point-by-point substitution of the PWM switch with its equivalent circuit. The proposed model is verified by simulation and experimental results of various converters, and compared with other models to demonstrate its accuracy. The proposed model is accurate up to half of switching frequency.

Constant on-time V$^2$ control for point-of-load Buck converters has instability issue in the cases that the output capacitors RC time constants are small. This paper intensively studies the proposed solution using capacitor current ramp compensation, which is a superior solution featuring fast response and universality. A frequency domain small signal model based on describing function method is proposed. The time domain large signal response to the load step change is analyzed. The analysis illustrates the unique transient response behaviors of the capacitor current ramp compensated V$^2$ control. The design optimization methodology based on frequency domain and time domain analysis is presented. The proposed model and the design guidelines are verified by the experimental results.

This article presents a scalable multiphase peak current-mode Buck controller with sub-milliohm direct current resistance (DCR) current sensing and synchronized overcurrent protection. Low DCR current sensing capability is critical in pursuing high efficiency and precise current balancing. For this purpose, a sub-milliohm DCR current sensing circuit is proposed. The low-frequency current signals from all the phases are amplified by a time-shared amplifier, and the outputs are combined with the exaggerated high-frequency signals, respectively, to rebuild the proportional current sensing signals. The small signal analysis and the design guidelines of the proposed sensing scheme are presented. The proposed current sensing scheme enhances the signal-to-noise ratio, improves the phase to phase current balancing, and dramatically reduces the silicon area of the sensing circuit. A latch-up problem of hiccup mode over current protection in the multi-chip parallel system is addressed in this article. A synchronized hiccup mode over current protection scheme is designed to solve the issue without adding extra communication bus to the system. The proposed controller is fabricated using a 0.6-μm BiCMOS process, and the experimental results prove the effectiveness of the current sensing circuit and protection scheme.

In order to incorporate the advantage of the V ² control scheme and the benefits of digital implementation, this paper proposes a digital V ² control with hybrid capacitor current ramp compensation, which includes the estimated output capacitor current ramp and the external ramp. Since capacitor current responds to the load change immediately, the proposed method has faster transient response than either digital inductor current compensation or external ramp compensation. The proposed estimator does not require high sampling rate and avoids the current ramp distortion due to the parasitic resistance and inductance. The small-signal model is derived by describing function to understand the dynamic characteristics of the proposed control scheme. The model provides design criteria of the current feedback gain and the external ramp slope. The effectiveness of the proposed control architecture and the current ramp estimator is verified by simulation and experimental results. Compared with the benchmark, the proposed control has 70% reduction on settling time and 20% reduction on undershoot deviation.

The conventional slope compensations for current mode controls do not take all the parameters’ changes into account, so the variations on small-signal transfer functions limit the voltage loop bandwidth (BW). In order to optimize the dynamic performance of current-mode control, this letter proposes a universal auto-tuning technique for external ramp slope based on the sensed slope of current feedback signal. The tuning mechanism keeps the quality factor of the double poles unchanged over the duty cycle variation, inductor tolerance, sensing element variation, and topology change, thus a consistent wide BW control is achieved without the limitation from the corner cases. Simple digital and analog implementations are proposed to realize the auto-tuning concept. This method is applicable to digital and analog current-mode controllers with peak current mode, valley current mode, and average current mode operations. The effectiveness of the proposed method is verified by simulation and experimental results.