Ship-radiated noise (SRN) recognition is vital for underwater acoustics, with applications in both military and civilian fields. Traditional manual recognition by sonar operators is inefficient and error-prone, motivating the development of automated recognition systems. However, most existing deep learning approaches demand high computational resources, limiting their deployment on resource-constrained edge devices. To overcome this challenge, we propose LW-MS-LFTFNet, a lightweight model informed by time-frequency analysis of SRN that highlights the critical role of low-frequency components. The network integrates a multi-scale depthwise separable convolutional backbone with CBAM attention for efficient spectral representation, along with two LSTM-based modules to capture temporal dependencies in low-frequency bands. Experiments on the DeepShip dataset show that LW-MS-LFTFNet achieves 75.04% accuracy with only 0.85 M parameters, 0.38 GMACs, and 3.27 MB of storage, outperforming representative lightweight architectures. Ablation studies further confirm that low-frequency temporal modules contribute complementary gains, improving accuracy by 2.64% with minimal overhead. Guided by domain-specific priors derived from time-frequency pattern analysis, LW-MS-LFTFNet achieves efficient and accurate SRN recognition with strong potential for edge deployment.

Random numbers play a vital role in modern information security, where quantum random number generators (QRNGs) based on single-photon avalanche diodes (SPADs) offer a promising physical platform for quantum random-number generation. However, practical SPAD QRNGs can exhibit temporal correlation arising from finite photon-event statistics and detector nonidealities. To overcome these limitations, this paper presents a high-speed, 256-channel SPAD QRNG chip, featuring a 256 × 512-pixel array integrated with a rolling-sampling time-division multiplexing architecture. By virtue of the rolling-sampling mechanism, the single-pixel sampling interval is extended to 40.96 μs, which substantially reduces the measured temporal correlation by increasing the per-pixel revisit interval while preserving aggregate throughput. Within one complete operating cycle, the chip generates 256 random bits simultaneously, achieving a maximum aggregate raw output bitrate of 3.2 Gb/s without digital post-processing. An FPGA-based test platform was constructed for experimental verification. Measurements demonstrate that under standard indoor illumination (8 W/m²), the generated raw bitstreams pass all 15 NIST SP 800–22 statistical randomness tests at 3.2 Gb/s without post-processing. Furthermore, under controlled 530 nm illumination, the measured lag-1 serial autocorrelation coefficient decreases below the 10⁻³ reference level at an incident optical power of 11.6 μW. The proposed chip offers a low-optical-power, high-throughput solution for integrated hardware security.