A dual-capture wide dynamic range CMOS image sensor using an in-pixel floating-diffusion (FD) storage capacitor is proposed. The proposed structure uses the FD as a storage capacitor. The potential of the FD node is read out using a floating-gate capacitor without a contact metallization of the FD node to reduce the leakage. The proposed sensor was fabricated using a 0.35-mum CMOS process. The chip includes 320 times 240 pixels whose pitch is 5.6 mum and whose fill factor is 36%. The measurement results show 100-dB dynamic range, and the leakage at the non-metalized FD is reduced to about one-third of that of the conventional FD with the contact metallization.

Despite the remarkable improvement of hardware and network technology, the inevitable delay from a user’s command action to a system response is still one of the most crucial influence factors in user experiences (UXs). Especially for a web video service, an initial delay from click action to video start has significant influences on the quality of experience (QoE). The initial delay of a system can be minimized by preparing execution based on predicted user’s intention prior to actual command action. The introduction of the sequential and concurrent flow of resources in human cognition and behavior can significantly improve the accuracy and preparation time for intention prediction. This paper introduces a threaded interaction model and applies it to user intention prediction for initial delay reduction in web video access. The proposed technique consists of a candidate selection module, a decision module and a preparation module that prefetches and preloads the web video data before a user’s click action. The candidate selection module selects candidates in the web page using proximity calculation around a cursor. Meanwhile, the decision module computes the possibility of actual click action based on the cursor-gaze relationship. The preparation activates the prefetching for the selected candidates when the click possibility exceeds a certain limit in the decision module. Experimental results show a 92% hit-ratio, 0.5-s initial delay on average and 1.5-s worst initial delay, which is much less than a user’s tolerable limit in web video access, demonstrating significant improvement of accuracy and advance time in intention prediction by introducing the proposed threaded interaction model.

Using a secondary device while viewing a primary device (i.e. TV), or media multitasking, is now common. Numerous researchers and practitioners have attempted to introduce secondary devices into education as a new learning environment providing additional information to the user. However, the learning-related effects of using a second screen remain controversial. This study examined the effects of second-screen-application use on attention, learning performance, and user experience per content relevance for three primary contents (PC; i.e. videos) requiring different amounts of cognitive load: low, medium, and high. Second-screen use reduced learning performance and user satisfaction when the PC required high cognitive load. However, participants exhibited increased learning performance, concentration, and satisfaction with the PC requiring medium-cognitive-load when highly relevant information was presented on the secondary screen simultaneously. Based on these findings, guidelines were suggested for designing a second-screen application without degrading users’ learning and experience.

A new sensitivity controllable pixel structure is proposed for CMOS active-pixel image sensor. The proposed pixel structure has a sensitivity control gate overlaid on the photodiode. The sensitivity of the pixel is controlled by the bias voltage of the control gate that forms a variable accumulation-mode MOS capacitor. The prototype sensor is fabricated with a 0.35-mum CMOS process and consists of 60 times 240 pixels with 5.6-mum pixel pitch. Measurement results show that the sensitivity of the photodiode can be controlled by a factor of 4.

Various self-powered devices employ energy-harvesting technology to capture and store an ambient energy. The photovoltaic (PV) cell is one of the most preferred approaches due to its potential for on-chip integration. Although serial connection of multiple PV cells is commonly required to obtain a sufficiently high voltage for circuit operation, a voltage boosting with serially stacked PV cells is limited in a standard bulk CMOS process because all the PV cells are intrinsically connected to the common substrate. It is possible to increase the output voltage by stacking multiple PV cells with a large area ratio between stages. However, nonoptimal design results in a poor conversion efficiency or a limited open-circuit voltage, making it unsuitable for practical applications. This article proposes a stacking structure and its optimal design method for PV cell stacking in a triple-well CMOS process. The proposed approach utilizes an additional current-sourcing photodiode and an optical filter, which allow high voltage generation without a significant efficiency degradation. The test chip with four-stage stacked PV cells was fabricated using a 0.25-μm standard triple-well CMOS process. The experimental results demonstrate an output voltage of 1.6 V and an electrical power of 263 nW/mm² under an incident illumination with an intensity of 96 μW/mm², achieving a responsivity of 1.91 mA/W and a conversion efficiency of 0.27%.