Enzyme engineering drives innovation in biotechnology, medicine, and industry, yet conventional approaches remain limited by labour-intensive workflows, high costs, and narrow sequence diversity. Artificial intelligence (AI) is revolutionising this field by enabling rapid, precise, and data-driven enzyme design. Machine learning and deep learning models such as AlphaFold2, RoseTTAFold, ProGen, and ESM-2 accurately predict enzyme structure, stability, and catalytic function, facilitating rational mutagenesis and optimisation. Generative models, including ProteinGAN and variational autoencoders, enable de novo sequence creation with customised activity, while reinforcement learning enhances mutation selection and functional prediction. Hybrid AI–experimental workflows combine predictive modelling with high-throughput screening, accelerating discovery and reducing experimental demand. These strategies have led to the development of synthetic “synzymes” capable of catalysing non-natural reactions, broadening applications in pharmaceuticals, biofuels, and environmental remediation. The integration of AI-based retrosynthesis and pathway modelling further advances metabolic and process optimisation. Together, these innovations signify a shift from empirical, trial-and-error methods to predictive, computationally guided design. The novelty of this work lies in presenting a unified synthesis of emerging AI methodologies that collectively define the next generation of enzyme engineering, enabling the creation of sustainable, efficient, and functionally versatile biocatalysts.

This paper presents three optimal-complexity structures (I, II, III) for pipelined distributed arithmetic (DA) based least-mean-square (LMS) adaptive filter. The complexity of proposed structures is reduced by implementing offset-binary-coding (OBC) combinations of input samples on hardware. However, some non-OBC outputs are produced, and subsequently eliminated in the error computation during the initial clock cycles. For achieving more performance benefits, radix-4 OBC combinations of input samples are implemented with the proposed partial product generators. In addition, novel low-complexity implementations for the offset term, weight update block and shift-accumulate unit are also proposed. Analysis shows that byte-complexity of proposed structures vary linearly with the order of DA base unit, while their bit-complexity depends on the topology. All the structures show significant hardware savings, Structure-I has least critical-path and Structure-II, III offer superior convergence performance. Experimental results show that the Structure-I, II and III with 32 nd order filter provide savings 71.13%, 71.83% and 73.08% in area, 68.47%, 70.01% and 72.17% in power, 51.74%, 37.83% and 45.38% in area-per-throughput (APT), 47.33%, 33.72% and 43.19% in power-per-throughput (PPT), 55.11%, 59.66% and 64.20% in slice LUTs, 35.33%, 40.28% and 44.87% in flip-flops over the best existing scheme.

Long short-term memory (LSTM) networks are extensively used in various sequential learning tasks, including speech recognition. Their significance in real-world applications has prompted the demand for cost-effective and power-efficient designs. This paper introduces LSTM architectures based on distributed arithmetic (DA), utilizing circulant and block-circulant matrix-vector multiplications (MVMs) for network compression. The quantized weights-oriented approach for training circulant and block-circulant matrices is considered. By formulating fixed-point circulant/block-circulant MVMs, we explore the impact of kernel size on accuracy. Our DA-based approach employs shared full and partial methods of add-store/store-add followed by a select unit to realize an MVM. It is then coupled with a multi-partial strategy to reduce complexity for larger kernel sizes. Further complexity reduction is achieved by optimizing decoders of multiple select units. Pipelining in add-store enhances speed at the expense of a few pipelined registers. The results of the field-programmable gate array showcase the superiority of our proposed architectures based on the partial store-add method, delivering reductions of 98.71% in DSP slices, 33.59% in slice look-up tables, 13.43% in flip-flops, and 29.76% in power compared to the state-of-the-art.

Distributed arithmetic (DA) is an efficient look-up table (LUT) based approach. The throughput of DA based implementation is limited by the LUT size. This paper presents two high-throughput architectures (Type I and II) of non-pipelined DA based least-mean-square (LMS) adaptive filters (ADFs) using two’s complement (TC) and offset-binary coding (OBC) respectively. We formulate the LMS algorithm using the steepest descent approach with possible extension to its power-normalized LMS version and followed by its convergence properties. The coefficient update equation of LMS algorithm is then transformed via TC DA and OBC DA to design and develop non-pipelined architectures of ADFs. The proposed structures employ the LUT pre-decomposition technique to increase the throughput performance. It enables the same mapping scheme for concurrent update of the decomposed LUTs. An efficient fixed-point quantization model for the evaluation of proposed structures from a realistic point-of-view is also presented. It is found that Type II structure provides higher throughput than Type I structure at the expense of slow convergence rate with almost the same steady-state mean square error. Unlike existing non-pipelined LMS ADFs, the proposed structures offer very high throughput performance, especially with large order DA base units. Furthermore, they are capable of performing less number of additions in every filter cycle. Based on the simulation results, it is found that $256^{\mathrm {th}}$ order filter with $8^{\mathrm {th}}$ order DA base unit using Type I structure provides $9.41 \times $ higher throughput while Type II structure provides $16.68 \times $ higher throughput as compared to the best existing design. Synthesis results show that $32^{\mathrm {nd}}$ order filter with $8^{\mathrm {th}}$ order DA base unit using Type I structure achieves 38.76% less minimum sampling period (MSP), occupies 28.62% more area, consumes 67.18% more power, utilizes 49.06% more slice LUTs and 3.31% more flip-flops (FFs), whereas Type II structure achieves 51.25% less MSP, occupies 21.42% more area, consumes 47.84% more power, utilizes 29.10% more slice LUTs and 1.47% fewer FFs as compared to the best existing design.

The next crucial step in artificial intelligence involves integrating neural network models into embedded and mobile systems. This requires designing compact and energy-efficient neural network models in silicon for optimized performance. This article introduces a unified approach for enhancing the architectural efficiency of long short-term memory (LSTM) recurrent neural networks (RNNs). Precisely, two new structures (I and II) based on the two’s complement (TC) digit-serial distributed arithmetic (DSDA) technique are presented. The block-circulant matrix–vector multiplications (MVMs) and element-wise multiplications (EWMs) are formulated using TC DSDA. In addition, a fixed-point (FxP) training procedure for quantized LSTM RNNs is considered and validated for speech recognition tasks. Both structures leverage the circular rotation of weights and generate partial products with input digit slices. A new partial-product generator (PPG) and partial-product selector (PPS) designed to work with both unsigned and signed digits is introduced. In Structure I, a nonpipelined MVM is realized with a few PPGs and PPSs, followed by a shift-accumulate unit (SAU). Conversely, in Structure II, a suitably chosen depth-pipelined MVM is achieved with multiple PPGs and PPSs, followed by a shift-to-add tree (SAT). A critical path delay (CPD) analysis for both the proposed structures is also presented. Compared with previous works, post-synthesis results on $28$ -nm fully depleted silicon-on-insulator (FDSOI) technology reveal that for a model size of $128$ $\times$ $128$ , Structures I and II provide $39.87\%$ , $95.63\%$ , and $30.95\%$ , $91.18\%$ more area and energy efficiencies, respectively.

This paper presents architectural trade-off analysis for accelerating two (Type I, II) fixed-point long short-term memory (LSTM) network based on circulant matrix-vector multiplications (MVMs) using radix- $r$ offset binary coding (OBC) scheme. Type I MVM architecture rotates the weights with the proposed modulo-cum interleaver and uses partial product generators (PPGs) with a single generation unit across a column. It is hardware-optimized using a single adder tree through time-multiplexing. Meanwhile, Type II MVM architecture rotates the inputs with the proposed store-cum interleaver and uses single PPGs with a single generation unit across a row. It is time-optimized by unfolding shift-accumulate unit to a shift-add tree followed by pipelining. A new design for element-wise multiplication using radix- $r$ PPG is also presented. Both the designs are extended to their block-circulant variants for certain accuracy requirements. Post-synthesis of Type I and II architectures for a different model, kernel, radix sizes and clock frequencies result in several efficient designs. Compared with the prior scheme, Type I architecture for $128 \times 128$ with $r=2$ on $28$ nm FDSOI technology at $800$ MHz occupies $32.27\%$ lesser area, consumes $67.89\%$ lesser power at the same throughput, while Type II architecture at the expense of area and power provides $40\times$ higher throughput.