Since sparse neural networks usually contain many zero weights, these unnecessary network connections can potentially be eliminated without degrading network performance. Therefore, well-designed sparse neural networks have the potential to significantly reduce the number of floating-point operations (FLOPs) and computational resources. In this work, we propose a new automatic pruning method--sparse connectivity learning (SCL). Specifically, a weight is reparameterized as an elementwise multiplication of a trainable weight variable and a binary mask. Thus, network connectivity is fully described by the binary mask, which is modulated by a unit step function. We theoretically prove the fundamental principle of using a straight-through estimator (STE) for network pruning. This principle is that the proxy gradients of STE should be positive, ensuring that mask variables converge at their minima. After finding Leaky ReLU, Softplus, and identity STEs can satisfy this principle, we propose to adopt identity STE in SCL for discrete mask relaxation. We find that mask gradients of different features are very unbalanced; hence, we propose to normalize mask gradients of each feature to optimize mask variable training. In order to automatically train sparse masks, we include the total number of network connections as a regularization term in our objective function. As SCL does not require pruning criteria or hyperparameters defined by designers for network layers, the network is explored in a larger hypothesis space to achieve optimized sparse connectivity for the best performance. SCL overcomes the limitations of existing automatic pruning methods. Experimental results demonstrate that SCL can automatically learn and select important network connections for various baseline network structures. Deep learning models trained by SCL outperform the state-of-the-art human-designed and automatic pruning methods in sparsity, accuracy, and FLOPs reduction.

The Ta/Ta₂O₅/AlN/graphene memristor with silicon-based multilayer graphene films as the bottom electrode has stable electrical characteristics.

Feature learning with deep neural networks has made remarkable progress in recent years. However, its data-driven nature makes the collection of labeled training data expensive or impossible when the testing domain changes. Here we propose a method of transferable feature learning and instance-level adaptation to improve the generalization ability of deep neural networks so as to mitigate the domain shift challenge for cross-domain visual recognition. When less labeled information is available, our proposed method shows attractive results in the new target domain and outperforms the typical fine-tuning method. Two deep neural networks are chosen as the representatives to be further developed with our proposed method, to do a comprehensive study about the generalization ability on the tasks of image-to-image transfer, image-to-video transfer, multi-domain image classification and weakly supervised detection. Experimental results show that our proposed method is superior to other existing works in the literature. In addition, a large scale of cross-domain database is merged from three different domains, providing a quantitative platform to evaluate different approaches in the field of cross-domain object detection.

The growing demand for high-performance ultra- high-definition video coding leads to H.265/HEVC, where the increased computational complexity and data/timing dependency hinder its coding throughput. To address these challenges, this paper presents four algorithm adaptations and a fully-parallel hardware architecture for H.265/HEVC intra encoder. To our best knowledge, this is the first fully-parallel H.265/HEVC intra encoder. This design supports 35 prediction modes and all CTU partitions. All PUs are independently processed in four prediction engines for high parallelism. An appropriate set of intra prediction modes, RDO candidates, and CABAC rate estimate instances is assigned to each PE, where internal computational tasks are pipelined and scheduled to maximize the processing throughput. Compared with the HM-15.0 software, the proposed algorithm adaptations lead to a reduction of 27% in computational workload, while the average BD-Rate and BD-PSNR are 4.39% and -0.21dB, respectively. This BD-Rate is lower than existing designs with the same video resolution. FPGA implementation of proposed design shows it operates at 120MHz and supports 45 fps of 1080P video sequences using 201K logic elements and 120KB on-chip SRAM. ASIC implementation of the proposed design in TSMC 90nm technology shows that its clock frequency reaches 320MHz with a hardware gate count of 2288K, and it supports real-time encoding of 30 fps of 4K video sequences. Compared with state-of-the-art designs, our proposed design demonstrates advantages in computational complexity, bit rate, video quality, throughput, reliability, and flexibility.

Singular value decomposition (SVD) is one of the most effective algorithms in recommender systems (RSs). Due to the iterative nature of SVD algorithms, one big challenge is initialization that has a major impact on the convergence and performance of RSs. Unfortunately, existing SVD algorithms in the literature typically initialize the user and item features in a random manner; thus, data information is not fully utilized. This work addresses the challenge of developing an efficient initialization method for SVD algorithms. We propose a general neural embedding initialization framework, where a low-complexity probabilistic autoencoder neural network initializes the features of user and item. This framework supports explicit and implicit feedback data sets. The design details of our proposed framework are elaborated and discussed. Experimental results show that RSs based on our proposed initialization framework outperform the state-of-the-art methods in rating prediction. Moreover, regarding item ranking, our proposed framework shows an improvement of at least 2.20% ~5.74% than existing SVD algorithms and other matrix factorization methods in the literature.

High computational complexity and heavy data/ timing dependency in HEVC hinder the throughput of video encoding. In order to address both design challenges, we present high-performance algorithm adaptations and high-throughput hardware architecture for HEVC intra encoders. Particularly, the chroma intra prediction includes the derived luma mode, which greatly improves the worst-case video compression performance. Compared with the HM-15.0 reference software, the proposed algorithms reduce the computational workload by 22%, while the average BD-Rate and BD-PSNR for classes A-F and 4K are 2.79% and -0.13dB, respectively. This BD-Rate is lower than existing designs in the literature with the same video resolution. The FPGA implementation of proposed design shows it operates at 120MHz and supports 45 fps of 1080P video sequences using 196K logic elements and 127KB on-chip SRAM. The ASIC implementation of the proposed design in TSMC 90nm technology shows that its clock frequency reaches 320MHz with a hardware gate count of 2186K and power consumption of 290mW, and it supports real-time encoding of 4K videos at 30 fps.