The most used asymmetric encryption algorithm nowadays is RSA. It may become insecure regarding advances in the field of quantum computers. It is the reason why the National Institute of Standards and Technologies introduces the challenges of choosing a new post-quantum encryption standard. Initially, NIST received 82 submissions comprising key encapsulation mechanisms and digital signature schemes. However, only 69 of them were formally accepted after an initial review. In July 2022, NIST selected some algorithms for standardization. For the key encapsulation mechanism, Kyber was selected, and for digital signatures, Dilithium Falcon and SPHINCS+. After the third round concluded, NIST indicated it would continue to evaluate some of the alternative algorithms that were not selected as finalists in the third round. This ongoing evaluation is informally referred to as a "fourth round." Initially, there were four participants - BIKE, Classic McEliece, SIKE, and HQC. However, the SIKE downfall with the Castryck-Decru attack was introduced in July 2022, and the HQC algorithm was chosen for standardization in March 2025. In our research, we examine all functions of BIKE, Classic McEliece, and the HQC from the point of view of time and memory consumption. The results obtained will help us during the implementation of the BIKE algorithm on ESP32.

Post-quantum cryptography represents one of the most promising areas of modern cryptography. The development in this discipline significantly accelerated after it became of interest to the National Institute of Standards and Technology (NIST). One of the important research directions in this area is the practical deployment of post-quantum cryptographic algorithms on resource-constrained devices. In this article, we investigate the possibility of deploying post-quantum cryptography on small processors with limited random access memory (RAM) capacity. These processors are commonly used in Internet of Things (IoT) devices, where the practical deployment of post-quantum algorithms remains challenging due to computational and memory constraints. We select a suitable algorithm and perform several implementation modifications that enable its execution on microcontrollers with limited memory resources.