The CMOS active pixel sensor (APS) operating in the logarithmic mode is the most common and useful CMOS wide-dynamic-range imager. Notwithstanding, fixed-pattern noise (FPN) between pixels compromises the quality of the image generated by the focal-plane array. Classical techniques as correlated double sampling do not work properly in this mode, and alternative techniques must be applied in order to calibrate FPN. The alternative techniques require either complex pixel circuitry, or external memory and software level calibration. Purposefully to improve image quality at reduced circuitry complexity, a new calibration technique is proposed that can be applied directly to the basic three-FET APS circuit. The efficacy of the proposed technique was experimentally verified with a small pixel array fabricated in a standard 0.35-$\mu \text{m}$ CMOS technology. The experimental results show a steady FPN attenuation within the whole tested illumination range and the improvement of the signal-to-noise and distortion ratio of the array.

The three FET CMOS active pixel sensors (APS) operating in the linear-logarithmic mode is one of the most efficient wide-dynamic-range imagers. However, the quality of the image generated at the focal-plane array is often compromised by fixed-pattern noise (FPN) between pixels. The classical correlated double sampling (CDS) technique is used to reduce FPN in imagers operating in the linear mode. But in the complementary linear-logarithmic mode CDS does not work properly and alternative techniques must be applied to reduce FPN. The ordinary alternative techniques increase either the complexity of the pixel or its external circuitry. In order to avoid these problems a new technique was devised to reduce FPN that can be applied to the basic three FET APS architecture. With the purpose to assert the efficacy of the proposed technique a small array was fabricated in a standard 0.35 μm CMOS technology. Experimental results show that the proposed technique is able to reduce FPN quite steadily within the whole illumination range used to test the array. And therefore, the signal-to-noise-and-distortion ratio (SNDR) of the array is also improved within the whole range of operation.

Proposal techniques that reduce financial costs in the diagnosis and treatment of animal diseases are welcome. This work uses some machine learning techniques to classify whether or not cases of canine visceral leishmaniasis are present by physical examinations. For validation of the method, four machine learning models were chosen: K-nearest neighbor, Naïve Bayes, support vector machine and logistic regression models. The tests were performed on three hundred and forty dogs, using eighteen characteristics of the animal and the ELISA (enzyme-linked immunosorbent assay) serological test as validation. Logistic regression achieved the best metrics: Accuracy of 75%, sensitivity of 84%, specificity of 67%, a positive likelihood ratio of 2.53 and a negative likelihood ratio of 0.23, showing a positive relationship in the evaluation between the true positives and rejecting the cases of false negatives.

Targeting 3D image reconstruction and depth sensing, a desirable feature for complementary metal oxide semiconductor (CMOS) image sensors is the ability to detect local light incident angle and the light polarization. In the last years, advances in the CMOS technologies have enabled dedicated circuits to determine these parameters in an image sensor. However, due to the great number of pixels required in a cluster to enable such functionality, implementing such features in regular CMOS imagers is still not viable. The current state-of-the-art solutions require eight pixels in a cluster to detect local light intensity, incident angle and polarization. The technique to detect local incident angle is widely exploited in the literature, and the authors have shown in previous works that it is possible to perform the job with a cluster of only four pixels. In this work, the authors explore three novelties: a mean to determine three of four Stokes parameters, the new paradigm in polarization cluster-pixel design, and the extended ability to detect both the local light angle and intensity. The features of the proposed pixel cluster are demonstrated through simulation program with integrated circuit emphasis (SPICE) of the regular Quadrature Pixel Cluster and Polarization Pixel Cluster models, the results of which are compliant with experimental results presented in the literature.

In recent years, many chaos-based encryption algorithms have been proposed. Many of these are based on established designs and populate their S-boxes with values derived from chaotic maps, following conventional implementation strategies to enable comparison with their original non-chaotic counterparts. In contrast, this work proposes a novel approach: a Chaos-Based Substitution Box (CB-SBox) implementation, in which conventional ROM-based S-boxes are replaced by a digital circuit that directly executes a selected chaotic map. This method enables the construction of S-boxes with long word lengths through an FPGA-based programmable circuit that allows for variable S-box lengths, facilitating the analysis of S-boxes of varying sizes, and ultimately enhancing security, particularly for larger S-boxes, as demonstrated by increased resistance to linear and differential cryptanalysis. Furthermore, the proposed CB-SBox achieves reductions in both area and power consumption compared to size-comparable ROM-based S-boxes. A 19-bit chaos-based S-box consumes just 0.0238% of the area and 0.0241% of the power required by an equivalent ROM-implemented S-box while providing the same level of security. The inherent unpredictability of non-linear chaotic behavior causes the proposed chaos-based S-boxes to exhibit non-bijective characteristics, making them well suited for application in non-invertible cryptographic primitives, such as hash functions and Feistel networks. The proposed CB-SBox is implemented in a Feistel network as described in the literature, and the results are provided.