Sn-based lead-free solders such as Sn-Ag-Cu, Sn-Cu, and Sn-Bi have been used extensively for a long time in the electronic packaging field. Recently, low-temperature Sn-Bi solder alloys attract much attention from industries for flexible printed circuit board (FPCB) applications. Low melting temperatures of Sn-Bi solders avoid warpage wherein printed circuit board and electronic parts deform or deviate from the initial state due to their thermal mismatch during soldering. However, the addition of alloying elements and nanoparticles Sn-Bi solders improves the melting temperature, wettability, microstructure, and mechanical properties. Improving the brittleness of the eutectic Sn-58wt%Bi solder alloy by grain refinement of the Bi-phase becomes a hot topic. In this paper, literature studies about melting temperature, microstructure, inter-metallic thickness, and mechanical properties of Sn-Bi solder alloys upon alloying and nanoparticle addition are reviewed.

In this study, the authors have reviewed recent advances on the transient liquid phase (TLP) bonding technology for various applications especially power module packaging in view of the recent increasing demand for the production of vehicles, smartphones, semiconductor devices etc. TLP bonding is one of the potential technologies from clean technology that can replace the Pb-base solder technology without causing any serious environmental issues. It is based on the concept of both brazing as well as diffusion bonding. During TLP bonding, the liquid phase is transiently formed at the bonding interface. At this point, the melting point of filler metal increases due to the diffusion of element which degrades the melting point from liquid phase to base metal. Subsequently, the bonding occurs by isothermal solidification at the bonding temperature of liquid phase. Here, after bonding, the melting temperature of the joint layer becomes higher than bonding temperature. This review introduces the various aspects of TLP bonding including its principle, materials, applications, advantages and properties in detail.

With the continuous miniaturization of electronic devices and the upcoming new technologies such as Artificial Intelligence (AI), Internet of Things (IoT), fifth-generation cellular networks (5G), etc., the electronics industry is achieving high-speed, high-performance, and high-density electronic packaging. Three-dimensional (3D) Si-chip stacking using through-Si-via (TSV) and solder bumping processes are the key interconnection technologies that satisfy the former requirements and receive the most attention from the electronic industries. This review mainly includes two directions to get a precise understanding, such as the TSV filling and solder bumping, and explores their reliability aspects. TSV filling addresses the DRIE (deep reactive ion etching) process, including the coating of functional layers on the TSV wall such as an insulating layer, adhesion layer, and seed layer, and TSV filling with molten solder. Solder bumping processes such as electroplating, solder ball bumping, paste printing, and solder injection on a Cu pillar are discussed. In the reliability part for TSV and solder bumping, the fabrication defects, internal stresses, intermetallic compounds, and shear strength are reviewed. These studies aimed to achieve a robust 3D integration technology effectively for future high-density electronics packaging.