This paper explores a low standby power 10T (LP10T) SRAM cell with high read stability and write-ability (RSNM/WSNM/WM). The proposed LP10T SRAM cell uses a strong cross-coupled structure consisting standard inverter with a stacked transistor and Schmitt-trigger inverter with a double-length pull-up transistor. This along with the read path separated from true internal storage nodes eliminates the read-disturbance. Furthermore, it performs its write operation in pseudo differential form through write bitline and control signal with a write-assist technique. To estimate the proposed LP10T SRAM cell’s performance, it is compared with some state-of-the-art SRAM cells using HSPICE in 16-nm CMOS predictive technology model at 0.7 V supply voltage under harsh manufacturing process, voltage, and temperature variations. The proposed SRAM cell offers 4.65X/1.57X/1.46X improvement in RSNM/WSNM/WM and 4.40X/1.69X narrower spread in RSNM/WM compared to the conventional 6T SRAM cell. Furthermore, it shows 1.26X/1.08X/1.01X higher RSNM/WSNM/WM and 1.71X/1.25X tighter/wider spread in RSNM/WM compared to the best studied SRAM cells. The proposed SRAM cell indicates 74.48%/1.41% higher/lower read/write delay compared to the 6T SRAM cell. Moreover, it exhibits the third-(second-) best read (write) dynamic power, consuming 29.69% (26.87%) lower than the 6T SRAM cell. The leakage power is minimized by the proposed design, which is 37.35% and 12.08% lower than that of the 6T and best studied cells, respectively. Nonetheless, the proposed LP10T SRAM cell occupies 1.313X higher area compared to the 6T SRAM cell.

Modern system-on-chip-based applications require low-power/energy SRAMs for long-term operation. To deal with this issue, near-threshold SRAM design is an effective approach. In this regard, this paper presents an energy-efficient single-ended 10T (SE10T) near-threshold SRAM. The proposed SE10T improves read stability and writability with the help of a built-in read-assist scheme and a power-gating technique, respectively, and reduces power/energy consumption by using single-ended read/write operation and stacking of transistors in the cell core. Simulation results in 32-nm CMOS technology at a 0.6 V show that the proposed design improves read stability/writability by $3.03\times /1.35\times $ , reduces leakage power by 46.09%, and offers improvements of 86.09%/88.81% and 73.82%/62.72% in read/write power and read/write energy, respectively, in comparison with the conventional 6T SRAM. The minimum operation voltage of the proposed design is the lowest ( $V_{min} =590$ mV), which is reduced by 41% compared to the conventional 6T. However, read/write delay in the proposed design is increased by $2.48\times /5.40\times $ due to being single-ended, and the layout area of the proposed design is $1.893~\mu \text{m}^{2}$ , which is $1.82\times $ larger than that of the conventional 6T.

This paper aims to explore the design of a novel highly stable low-energy 10T (SLE10T) SRAM cell for near-threshold operation. The latch core of the proposed design consists of a cross-coupled structure of a tri-state inverter and a standard inverter. The tri-state inverter is switched to the high-impedance mode during a write operation to temporarily float the data node, improving writability. In addition, read stability is equivalent to hold stability due to considering a separate path for read current flow, as well as a built-in read-assist scheme to force the ‘0’ storing node to ground. Leakage and dynamic power consumptions in the designed cell are reduced with the help of single-bitline structure and stacking of transistors. The simulation results in a 7-nm FinFET at a 0.5 V show that the SLE10T improves read stability by at least 1.31 $\times$ compared to read-disturbance SRAMs and offers the second-highest writability, improvement of at least 1.10 $\times$ . Leakage power dissipation is reduced in the SLE10T by at least 1.10 $\times$ . Moreover, it improves read/write energy by at least 1.01 $\times$ /1.03 $\times$ . However, the area of the SLE10T bitcell is 0.02 $\mu$ m $^{2}$ , which is 1.657 $\times$ /1.318 $\times$ larger than the conventional 6T/8T bitcell.