Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Pohang 790-784, Korea
Prof. Dr. Byoung Hun Lee
Center for Semiconductor Technology Convergence, Department of Electrical Engineering, Pohang University of Science and Technology, Pohang 790-784, Korea
We demonstrate an advanced ReRAM based analog artificial synapse for neuromorphic systems. Nitrogen doped TiN/PCMO based artificial synapse is proposed to improve the performance and reliability of the neuromorphic systems by using simple identical spikes. For the first time, we develop fully unsupervised learning with proposed analog synapses which is illustrated with the help of auditory and electroencephalography (EEG) applications.
There is significant interest in synthesizing large-area graphene films at low temperatures by chemical vapor deposition (CVD) for nanoelectronic and flexible device applications. However, to date, low-temperature CVD methods have suffered from lower surface coverage because micro-sized graphene flakes are produced. Here, we demonstrate a modified CVD technique for the production of large-area, continuous monolayer graphene films from benzene on Cu at 100–300 °C at ambient pressure. In this method, we extended the graphene growth step in the absence of residual oxidizing species by introducing pumping and purging cycles prior to growth. This led to continuous monolayer graphene films with full surface coverage and excellent quality, which were comparable to those achieved with high-temperature CVD; for example, the surface coverage, transmittance and carrier mobilities of the graphene grown at 300 °C were 100%, 97.6% and 1,900–2,500 cm2 V−1 s−1, respectively. In addition, the growth temperature was substantially reduced to as low as 100 °C, which is the lowest temperature reported to date for pristine graphene produced by CVD. Our modified CVD method is expected to allow the direct growth of graphene in device manufacturing processes for practical applications while keeping underlying devices intact.
Feasibility of a high speed pattern recognition system using 1k-bit cross-point synaptic RRAM array and CMOS-based neuron chip has been experimentally demonstrated. Learning capability of a neuromorphic system comprising RRAM synapses and CMOS neurons has been confirmed experimentally, for the first time.