The memristor-based convolutional neural network (CNN) gives full play to the advantages of memristive devices, such as low power consumption, high integration density, and strong network recognition capability. Consequently, it is very suitable for building a wearable embedded application system and has broad application prospects in image classification, speech recognition, and other fields. However, limited by the manufacturing process of memristive devices, high-precision weight devices are currently difficult to be applied in large-scale. In the same time, high-precision neuron activation function also further increases the complexity of network hardware implementation. In response to this, this paper proposes a configurable full-binary convolutional neural network (CFB-CNN) architecture, whose inputs, weights, and neurons are all binary values. The neurons are proportionally configured to two modes for different non-ideal situations. The architecture performance is verified based on the MNIST data set, and the influence of device yield and resistance fluctuations under different neuron configurations on network performance is also analyzed. The results show that the recognition accuracy of the 2-layer network is about 98.2%. When the yield rate is about 64% and the hidden neuron mode is configured as −1 and +1, namely ±1 MD, the CFB-CNN architecture achieves about 91.28% recognition accuracy. Whereas the resistance variation is about 26% and the hidden neuron mode configuration is 0 and 1, namely 01 MD, the CFB-CNN architecture gains about 93.43% recognition accuracy. Furthermore, memristors have been demonstrated as one of the most promising devices in neuromorphic computing for its synaptic plasticity. Therefore, the CFB-CNN architecture based on memristor is SNN-compatible, which is verified using the number of pulses to encode pixel values in this paper.

Volatile programmable metallization cell is a promising threshold switching selector with excellent characteristics and simple structures. However, the large variation of threshold voltage is a major problem for practical application. In this work, we propose a dual-layer structure to increase selectivity and improve the threshold voltage variation. Compared to single-layer devices, this dual-layer device exhibits higher selectivity (>10⁷) and better threshold voltage uniformity with less than 5% fluctuation during 200 DC switching. The improvement is attributed to good control on the location of the filament formation and rupture after introducing a HfO₂ layer. It is deduced that a major factor consists of the difference of Ag ions mobility between SiTe and HfO₂ due to the grain boundary quantity.

The RRAM-based accelerators have become very popular candidates for neural network acceleration due to they perform matrix-vector multiplication in-memory with high storage density and low latency. Many related works have used fixed-precision quantization to achieve the model compression and enhance the tolerance of process variation, but these methods still suffer a large accuracy degradation and poor robustness to nonideal effects. In this work, we propose a crossbar-aware mixed-precision quantization scheme, which enables to search for the optimal precision of each part of the network as a way to improve the accuracy and robustness to noise. First, we introduce a group quantization strategy that can flexibly adjust the group size dynamically according to the crossbar size. Then, we propose a detailed mixed-precision search flow to search for the optimal precision set of the network. Finally, we give a noise injection adaption training method to enhance the tolerance of noise. Experimental results show that our proposed method can improve inference accuracy by at least 2.04% compared to the fixed-precision quantization under the same resource cost. The searched architecture with the highest accuracy most accurate (MA) could achieve an accuracy of 92.39% and a resource saving of 93.30% compared to the full precision model. The searched architecture with the biggest resource savings most efficient (ME) could achieve an accuracy of 91.11% and a resource saving of 95.57% compared to the full precision model. And, the average precision of the ME mixed-precision architecture is only 1.4 bits. Besides, the results show the mixed-precision network with noise adaption training is more robust to noise than the fixed-precision network with noise adaption training.

As one of the most promising methods in the next generation of neuromorphic systems, memristor-based spiking neural networks (SNNs) show great advantages in terms of power efficiency, integration density, and biological plausibility. However, because of the nondifferentiability of discrete spikes, it is difficult to train SNNs with gradient descent and error backpropagation online. In this article, we propose an improved training algorithm for multilayer memristive SNN (MSNN) with three methods spontaneously, supporting in situ learning in hardware: 1) temporal order encoding is applied to generate different pulse trains in neurons; 2) a simplified homeostasis is realized by the activation state and refractory period to regulate hidden neurons spontaneously; and 3) spiking-timing-dependent plasticity (STDP) in memristive synapses is adopted to update weights in situ . Correspondingly, we provide a circuitry example and verify it in LTSPICE. Then the MSNN is benchmarked with the MNIST data set and analyzed with visualization methods, showing better recognition accuracy (95.15%) than existing SNNs with comparable scales and bio-inspired learning rules. We also consider some nonideal effects in memristor crossbar array and peripheral circuits. Evaluation results show that the proposed MSNN is robust to finite resolution, circuit noise and writing noise; and larger network scale will help the MSNN alleviate the negative impacts of other nonideal factors, including yield and device-to-device variation. Moreover, the energy efficiency of a MSNN system is estimated to achieve 7.6TOPS/W, showing great potential in low-power applications.

This paper proposes Full-Parallel Convolutional Neural Networks (FP-CNN) for specific target recognition, which utilize the analog memristive array circuits to carry out the vector-matrix multiplication, and generate multiple output feature maps in one single processing cycle. Compared with ReLU and Tanh function, we adopt the absolute activation function innovatively to reduce the network scale dramatically, which can achieve 99% recognition accuracy rate with only three layers. Furthermore, we propose a performance metrics function to resize the scale of the FP-CNN for solving different classification tasks. With the help of such design guidelines, the FP-CNN can still achieve over 96% recognition accuracy under the condition of 95% yield of memristor crossbar array and 0.5% Single-Pole-Double-Throw switches (SPDT) noise.