Fully integrated high spectral purity photon-pair sources represent critical core components for scalable photonic quantum information processing systems. While micro-ring resonator based single-photon sources demonstrate superior integration capabilities, their spectral purity typically suffers from a theoretical upper bound below 92% in the absence of narrow-band spectral filtering, rendering it inadequate for advanced quantum applications. This work successfully implements an on-chip dual-pulse controlled photon pair generation architecture on a complementary metal oxide semiconductor (CMOS) compatible silicon photonic platform, achieving high spectral purity exceeding 98% by optimizing the beam splitting ratio and adjusting the relative time delay between the two pulses. Furthermore, to mitigate operating point drift in the micro-ring photon-pair generator induced by micro-heater current variations during testing, we developed a power control algorithm that locks the micro-ring resonance to the corresponding frequency of the shaped optical pulse, significantly improving long-term system stability.

We demonstrate a disaggregated optically-connected memory (OCM) architecture that supports dynamic resource allocation. Our proposed architecture utilizes a hitless wavelength-selective switch (WSS) based on silicon photonic (SiP) micro-ring resonators (MRRs) embedded with an equal-armed Mach-Zehnder interferometer, which permits a hitless rerouting of multi-wavelength signals. Error-free operation is achieved between a CPU node and two remote memory nodes using silicon photonic switch fabrics, showing the potential of integrating the photonic switched optically connected memory pools to the large-scale data centers and high performance computing (HPC) systems.

We propose and demonstrate an optically-connected memory(OCM) architecture with a nonblocking 4 × 4 optical switch based on dual-microring resonators, which can build links freely without any blocking, and disaggregates memory from computation node.

The non-deterministic nature of photon sources poses a fundamental challenge to scaling single-photon quantum processors. While multiplexing in space, time, and frequency can enhance heralding efficiency, key bottlenecks remain in the efficiency of the on-chip resource unit and the speed of the external control system. Here, we demonstrate a high-count-rate, spatially multiplexed single-photon source on a silicon chip. By implementing a bidirectional pumping scheme, our architecture halves the number of required photon sources, creating a compact, optimized unit for future large-scale multiplexing sources. In addition, we implement a control system based on a Random-Access Memory First-In-First-Out module to improve the count rate limitation. Experimental results demonstrate a coincidence count rate gain of 1.67 under both pulsed and continuous-wave pumping regimes in our system. This work provides a scalable unit design and a robust control strategy for high-rate quantum photonic circuits.

Photonic integrated switches with simultaneous space and wavelength selectivity represent a transformative technology for high-throughput data-center interconnection and scalable quantum networking. Silicon-based integrated switches are particularly compelling due to their ultra-compact footprints and high-density integration capabilities. However, achieving scalable non-blocking operation remains challenging because of interconnect-driven footprint expansion that grows rapidly with system size. While conventional hybrid spatial-spectral switches (HSSs) can reduce individual unit dimensions, they require M N (2 log ₂ N −1)/2 switching elements for an N × N × M λ configuration, creating a fundamental scalability bottleneck. To address this limitation, we propose and experimentally demonstrate a novel HSS architecture based on bandpass ring-assisted asymmetric Mach–Zehnder interferometers (RAMZIs) with a 3 dB bandwidth of 1.54 nm. Implemented on a silicon-on-insulator (SOI) platform, we realize a compact 4×4×2 λ HSS using only six such elements (versus 12 in a conventional design), occupying a footprint of just 0.38 mm ² while supporting data transmission rates exceeding 8×30 Gb /s. Crucially, the architecture can be further extended to N × N × M λ configurations with an efficient scaling factor of N ( M log ₂ N −1)/2. To our knowledge, this work delivers the most compact spatial-spectral switching system demonstrated to date, establishing a new benchmark for both scalability and efficiency in optical switching. These advances open pathways toward large-scale, high-performance switching solutions essential for next-generation data centers and quantum communication networks.