This paper introduces a hardware/software co-designed 3D object detection pipeline based on the PointPillars architecture for low-power embedded MPSoC deployment. The proposed system accelerates the computationally intensive stages in programmable logic (PL), including ROI filtering, coordinate transformation, pillarization, centroid extraction, and INT8 neural inference, using Vitis high-level synthesis (HLS) and an integrated Deep Learning Processing Unit (DPU). Control-oriented and irregular operations, such as data acquisition, Direct Memory Access (DMA) control, lightweight Non-Maximum Suppression (NMS), visualization, and logging, remain on the processing system (PS). The design targets the AMD Kria KV260 platform and achieves an accelerated core pipeline latency of 11.4 ms per frame at 300 MHz, corresponding to 87.4 Hz throughput, with 6.842 W board-level power consumption. Including PS-side NMS, the practical end-to-end latency is approximately 12.2 ms for typical KITTI scenes. Compared with existing Field-Programmable Gate Array (FPGA)-based implementations implementations, the proposed design reduces latency by up to $33\times$. It achieves a $202\times$ improvement in on-chip BRAM efficiency across HLS optimization versions through FIFO streaming, dataflow execution, and array partitioning. Experimental validation on physical hardware confirms that the proposed PL-accelerated hardware/software co-design provides a practical and cost-effective solution for real-time 3D LiDAR perception on embedded FPGA platforms.

This paper presents a hardware–software co-design framework for real-time super-resolution (SR) of low-quality video on resource-constrained edge platforms. At its core is a compact residual network obtained by once-for-all (OFA) neural architecture search over the Residual Channel Attention Network (RCAN) design space, trained conventionally and then optimized with quantization-aware training (QAT) for deployment on an integer-only deep-learning processing unit (DPU). Loop tiling and data-flow scheduling are applied within a custom high-level synthesis (HLS) pre-processing pipeline that feeds the DPU, and a per-directive ablation isolates the contribution of each optimization to post-route resource usage and timing. Deployed on a Kria KV260 board with a $128\times 128$ network input, the INT8 network sustains $96.37$ FPS at the ×2 scale at a measured board power of $5.38$ W, corresponding to $6.32$ Mpixel/s of reconstructed output at $1.17$ Mpixel/J, within 63.2% of the device LUT budget and with timing closed at 275 MHz. Relative to the FP32 model, INT8 quantization costs $0.274$ dB of peak signal-to-noise ratio (PSNR) on Set5, $0.172$ dB on Set14, $0.116$ dB on B100, and $0.146$ dB on Urban100, a loss dominated (81–90%) by activation rather than weight quantization. On a held-out UAV subset drawn from VisDrone2019, which is the operating domain the system targets, the network reconstructs at $25.94$ dB and $0.748$ SSIM. These results show that a twenty-three-layer residual SR network can be deployed within a 5.38 W envelope on a low-cost integer-only edge FPGA, making the approach suitable for autonomous systems, robotics, and airborne surveillance.