Wirelessly powered implants are increasingly being developed to interface with neurons in the brain. They often rely on microelectrode arrays which are limited by their scalability and long-term stability because of their physical size and rigid configuration. Yet some clinical and research applications prioritize a distributed neural interface over one that offers high resolution. One solution to make large scale, fully specifiable, electrical stimulation/recording possible, is to disconnect the electrodes from the base, so that they can be arbitrarily placed, using a syringe, freely in the nervous system. In this work, a wirelessly powered stimulating implant is miniaturized using a novel electrode integration technique, and its implanted depth maximized using innovative optimization design methods for the transmitter and receiver coils. The stimulating device is implemented in a 130nm CMOS technology with the following characteristics: 300 μm × 300 μm × 80 μm size; optimized wireless powering; and integrated circuit, electrodes and coil. The wireless and stimulation capability of the implant is validated in a conductive medium and in-vivo. To the best of our knowledge, the fabricated free-floating miniaturized implant has the best depth-to-volume ratio making it an excellent tool for minimally-invasive scalable neural interface, and thus could eventually replace the rigid arrays that are currently the state-of-the-art in brain set-ups.

In this paper, an alternating current (ac) computing methodology is proposed for integration into wirelessly powered devices, such as radio-frequency (RF) tags and sensor nodes. Contrary to the traditional platforms that integrate direct current (dc)-powered computational logic along with the rectification and regulation stages, in the proposed approach, the harvested RF signal is directly used to power the data processing circuitry by leveraging the charge-recycling and adiabatic circuit theory. A near-field-based wireless power harvesting system with an 8-bit arithmetic logic unit is developed to evaluate the proposed framework. Simulation results in 45-nm technology demonstrate that the overall power consumption can be reduced by up to 16 times as compared to the conventional approach that relies on ac-to-dc conversion and static CMOS logic. This reduction in power enables significant computation capability for the RF-powered devices. Several important characteristics, such as the impact of circuit size on overhead and processing power, impact of voltage scaling on circuit operation, and power consumption, are investigated. Some important design issues and related tradeoffs are also discussed.