CRYSTALS-Kyber and CRYSTALS-Dilithium are representative lattice-based post-quantum cryptographic schemes, where number theoretic transform (NTT), inverse NTT (INTT), and point-wise multiplication (PWM) dominate polynomial arithmetic. Existing hardware accelerators are typically optimized for a single scheme or operation, resulting in limited scalability and redundant hardware resources. This paper presents a unified and scalable NTT/INTT/PWM architecture for both Kyber and Dilithium. A configurable two-dimensional processing-element (PE) array combined with an EVEN/ODD ping-pong memory organization enables conflict-free memory access and partial inter-stage pipelining. A unified K-RED-based modular multiplier supports either one Dilithium multiplication or two parallel Kyber multiplications using the same DSP resources, while PWM is mapped onto the existing PE array without requiring a separate complete PWM arithmetic array. Experimental results on a Xilinx Artix-7 FPGA show that the proposed modular multiplier reduces LUT utilization by 39.8% compared with the previous unified Kyber/Dilithium design. Under matched PE configurations, the proposed architecture achieves ATP reductions of up to 79.5% for Dilithium NTT/INTT and 73.9% for Kyber NTT/INTT, while the Kyber/Dilithium PWM mode achieves an ATP reduction of up to 78.3%. These results demonstrate that the proposed architecture provides an efficient, scalable, and highly reusable hardware solution for lattice-based post-quantum cryptographic accelerators.